Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Recent content by radar08

  1. R

    A Matlab Program to generate Xilinx .coe File.

    xilinx coe file In fact, to generate Xilinx coe file is to transform decade to binary of hex data. Matlab is very helpful. When using Xilinx IP Core to generate RAM with initialization file or ROM with .coe file, the top two line is: MEMORY_INITIALIZATION_RADIX=2...
  2. R

    course for FPGA architecture

    fpga course india http://www.ecs.umass.edu/ a good website.
  3. R

    [SOLVED] Read from a Text File, urgent help needed.

    hello, you can use UltraEdit to select the expected column.
  4. R

    design CIC and compansation FIR filters

    design cic you can download some paper from IEEE which can help you much. An economical class of digital filters for decimation and interpolation.pdf This paper is a good paper and it introduces CIC filter first.
  5. R

    puting hex file into VHDL written rom

    Re: rom hex file hello, you can use matlab which can help you to convert decimal integer to hex format and write into a file with the vendor needed format. the matlab function: dec2hex can help you. good luck.
  6. R

    Vhdl Answers to Frequently Asked Questions needed!!!

    me too. thanks^^^^^^
  7. R

    help in vhdl code.... no signal is generating

    Re: help in vhdl code....... 2 : process(CLK) ---sensitive but you donot use it in your process. begin if ( ADS_N ='0') then if(LA = "11") then COUNT <= TRUE; else COUNT <= FALSE; end if; end if ; if (COUNT = TRUE )then CNT <= CNT + 1; end if; end process X2; --signal generation...
  8. R

    help reagrding Decimation FIR on FPGA

    hello the fir coefficients are decided by factors list below: 1. sample rate; 2. band width of expected signal; 3. decimation factor you can get some information from GC1012a.pdf which is a userguide of GC1012. GC1012 is a special DDC(Digital Down Converter) chip.
  9. R

    LMS using FPGA - vhdl coding for LMS adaptive filters

    lms using fpga Xilinx Training Data: DSP Primer diplays the information on LMS using FPGA.
  10. R

    Help me convert a Verilog code to VHDL

    v2v synapticad X-HDL is very helpful. you can try it.
  11. R

    timing analysis ? - request for resources

    Re: timing analysis ? Of course, timing analysis is very important for a project. It can help you to find out if the project can work on your expected frequency.
  12. R

    fifo of xilinx(.vhd) 511 words of 36 bits, 127 words 64 bits

    Re: FIFO Please use Xilinx FIFO IP core, which is very easy to modify parameter such as width and depth.
  13. R

    Can i use spyglass with netlist after synthesis?

    Re: with spyglass What is the main function of spyglass?
  14. R

    RTL to schematic without synthesis

    topweaver maybe please try
See more

Part and Inventory Search

Back
Top