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Recent content by rac70

  1. R

    Difference b/w asynchronous Vs synchronous FIFO

    yes i am building it in simulink, Even i am checking the whole address like the conditions are (read_addr[8:0] == write_addr[8:0]) empty is enabled. and ((read_addr[7:0]==write_addr[7:0])&&(read_addr[8]^write_addr[8])) then pop is enabling. Here for 8 bit data i am adding an extra bit for...
  2. R

    Difference b/w asynchronous Vs synchronous FIFO

    Thank you for the info. Actually i had generated my read address and write address then i am using the conditions of MSB's to check whether it is empty or full for synchronous fifo. When i wanted to use the same logic for asynchronous fifo adding delays for write address and read address will...
  3. R

    Difference b/w asynchronous Vs synchronous FIFO

    Can you tell me, what is the main difference between synchronous and asynchronous fifo as per the design!! Does usage of gray counter alone in design makes all the sense for asynchronous design? I am having this doubt can anyone clarify...
  4. R

    Replicated logic optimization

    As FVM said, It is same logic , but different signals are used. The functionality was same, but each always block constitute the same functionality w.r.to their data presence at valid signal. The problem is the duplication of same logic for 6 times. will there be any chance of...
  5. R

    Replicated logic optimization

    There were many blocks pointing the same scenario here. As you said the logic utilization will be 6-times, can there be a solution for reducing the complexity of code , due to the replications the code size also got increased.
  6. R

    Replicated logic optimization

    Hi all, My RTL code contains exact 6 replications of same logic as it includes 6 different buffers. So, the code complexity was getting increased. I tried, using common function for the logic, but even the device utilization was the same. Can there be a better way to design? Waiting for your...
  7. R

    Remove padded bytes of zeros

    Hi all, how to remove the extra padded bytes of zeros when every time the bytes of zeros padded may lie b/w 1 to 16 suggest any logic?
  8. R

    Different widths of data on same bus

    Hi, thankyou but on the same bus can i send the data byte by byte instead of word by word which is advantageous..
  9. R

    Different widths of data on same bus

    thank you, here the design uses axi interface, actually the case is like the data is of 128 bit width and mic is of 64 width can i pass both of them on same bus or need to pad zeros for mic to make it 128 bit width.
  10. R

    Implementing an AES cryptographic algorithm

    yes, mostly you can find verilog cores, if you want to understand the AES implementation NIST FIPS 197 is the standard documentation.
  11. R

    Different widths of data on same bus

    Hi all, anyone help me in finding the logic for passing different widths of data on same bus
  12. R

    Implementing an AES cryptographic algorithm

    there are so many cores in opencores which are supporting 128 bit but they are with out any modes, under the name of crypt to core.
  13. R

    parallel execution of data

    haa that's true.. development board is fpga
  14. R

    parallel execution of data

    hi, anyone help me with this parallel execution. i had x bytes of data which is of very huge size, in that data i have to take each 16 bytes of data and perform xor operation with aes encrypted counter. here for each case the counter gets incremented and i.e encrypted. that particular...
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