Different widths of data on same bus

[rac70]

Hi all,
anyone help me in finding the logic for passing different widths of data on same bus

 

[TrickyDicky]

You cant, the bus width is fixed. depending on the interface there may be extra byte enable signals to mark specific bytes as not valid. But what interface are you using?

 

[rac70]

You cant, the bus width is fixed. depending on the interface there may be extra byte enable signals to mark specific bytes as not valid. But what interface are you using?

thank you,
here the design uses axi interface, actually the case is like the data is of 128 bit width and mic is of 64 width can i pass both of them on same bus or need to pad zeros for mic to make it 128 bit width.

 

[wtr]

If I understand your question correctly.

send the 128 bit signal

then just snippet the relevant stuff such that

-- initialize
sig_a <= (others => '0')

-- assign
sig_a(63 downto 0) <= stuff_i_care_about;

then when sampling

-- retrieve
stuff_wanted <= sig_a(63 downto 0);

-------------------------------
Edit
-------------------------------
Axi is an interface provided by Xilinx and therefore if the components want 128 bit then keep that.

 

[TrickyDicky]

thank you,
here the design uses axi interface, actually the case is like the data is of 128 bit width and mic is of 64 width can i pass both of them on same bus or need to pad zeros for mic to make it 128 bit width.

Axi Streaming I assume?
This is going to depend on what you want to do with it, and will depend on what format the downstream device requires.
You could zero pad and set tkeep/tstrb to mark the valid bytes, and then the downstream device can extract the data appropriatly. But this would be rather innefficient.
Or you could mux the data together (ie. put 2 64 bit words into a single word), and you could run the 128 bit bus at half the clock speed. (good efficiency)

But how you do it depends.

Axi is an interface provided by Xilinx and therefore if the components want 128 bit then keep that.

Axi is defined by ARM and Xilinx have chosen to use the specification in most of their new IP.

 

[xtcx]

Or you could mux the data together (ie. put 2 64 bit words into a single word), and you could run the 128 bit bus at half the clock speed. (good efficiency)

Axi is defined by ARM and Xilinx have chosen to use the specification in most of their new IP.

clocking two 64-bit words into one 128-bit word, unless the peer is a custom design it will not work. Also the AXI interface bus width can be configured to 64/32 bits wide as well instead.

 

[rac70]

clocking two 64-bit words into one 128-bit word, unless the peer is a custom design it will not work. Also the AXI interface bus width can be configured to 64/32 bits wide as well instead.

Hi,
thankyou but on the same bus can i send the data byte by byte instead of word by word which is advantageous..

 

[wtr]

thankyou but on the same bus can i send the data byte by byte instead of word by word which is advantageous..

In that case
Use a fifo with 128 bit input & 8 bit output?

This can easily be done using vendor ip.

You have to read 16 times faster than you write otherwise the fifo will overflow.

 

[xtcx]

Hi,
thankyou but on the same bus can i send the data byte by byte instead of word by word which is advantageous..

Yes you can. But the reading entity should also be aware of the lane positions (out of 128bit) that you are writing to. Agreeing mutually this can be done but potentially you are wasting 50% of performance