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Recent content by qtommer

  1. Q

    Question about verilog timescale settings.

    hey thank you all for the replies.. indeed i did it in testbench and everything works now..thank you all for your help! :)
  2. Q

    Question about verilog timescale settings.

    hi thanks for your reply tried it, the same error still occurs... ** Error: ~~~~~ v(23): near "#": syntax error, unexpected '#'
  3. Q

    Question about verilog timescale settings.

    hi there, the following is the code using generate,endgenerate to achieve an n bit adder. For now, the code sets n=4 thus having a 4 bit adder. The code is working fine. As you can see in the code, there is no timescale used, I would like each sample to be 100ns long in the waveform viewer. I...
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