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Recent content by pythonlong

  1. P

    what is HFN syntheisis in CTS?

    clock is diferent from other HFN. latency,transition,uncertainty can effect chip
  2. P

    Verilog/VHDL editor in linux

    vhdl editor windows emacs **broken link removed**
  3. P

    Synopsys DC chip synthesis workshop!

    chip synthesys workshop hope someone taken Sys Workshop could share the materials..
  4. P

    what is HFN syntheisis in CTS?

    hfn synthesis HFN constains three type: 1.clock 2.reset 3.general purpose solution: 1.set_ideal_network (-no_propagate) or set_dont_touch_network 2.set high_fanout_net_threshold,high_fanout_net_pin_capacitance when use dc,then insert buffer wen APR use Astro or Encounter a paper of SNUG
  5. P

    a APR problerm of Synopsys Astro

    astrol apr willing to help but unable to do so
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