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Recent content by Puppet123

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    Analog on Top Flow in Cadence EDA Tools

    Sure, it is all described here by Cadence: https://www.cadence.com/ko_KR/home/solutions/mixed-signal-solutions/mixed-signal-implementation.html Analog on Top Flow and Digital on Top Flow.
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    Analog on Top Flow in Cadence EDA Tools

    Looking for any resources on Analog on Top Flow using Cadence EDA Tools. Can you share any ? Thank you.
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    Want to EM Simulation a short circuited Tline as an inductor element

    I Want to run an EM Simulation a short circuited Tline as an inductor element using Momentum, a piece of microstrip to use it as an inductor of very low inductance as the kit of the process I use doesnt have an inductor so small (under 100pH). How to I set up the ground and signal ports and...
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    Placing Resistor and Capacitors in NWell In Layout

    To reduce noise coupling it is said to put resistors and capacitors in nwell in layout. What is nwell tied too ? Is nwell also surrounded by nwell guard ring? So what is nwell guard ring connected to ? It should be quiet - so analog ground ? The application is for a SAR ADC's capacitive...
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    Verilog A Based Differential Input, Differential Output Sample and Hold Circuit

    I am looking for an ideal Verilog-A Based Differential Input, Differential Output Sample and Hold Circuit for use in a Flash ADC simulation. Do you know where I can get one ? Is this included in the analog lib or ahdl lib libraries in the Cadence Virtuoso Platform / Spectre simulator ? Thanks.
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    RFIC Layout - Transmission Line

    Doesnt it depend on the distance and the design. I mean in an LNA with a lot of inductors dont you need transmission lines due to the distance between inductors at say 5-30 GHz ?
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    RFIC Layout - Transmission Line

    In RFIC Layout - or > 1GHZ RF IC Layout, when do you use a transmission line versus just using metal interconnect like in lower frequency design ? Is there a rule of thumb ?
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    .tek file for ASITIC for IBM 8RF-DM 130nm PDK

    Does anyone have the .tek file for ASITIC for the 130nm CMOS IBM 8RF-DM PDK - ibm_8rf_dm.tek ?
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    Biasing of Inverter for LNA

    I want to bias the circuit shown as an LNA. Output is between M2 and M3. It is a Class AB LNA and it uses extra N and PMOS transistors to provide extra gain for lower noise figure. What type of bias circuit would I use to bias it ?
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    [SOLVED] Good Advanced Level (Graduate) Text on Verilog/SystemVerilog with Examples

    Sorry I was not clear - I meant a book that has examples of advanced digital blocks implemented in verilog or system verilog code - by advanced - I mean microprocessor blocks or dsp blocks.
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    [SOLVED] Good Advanced Level (Graduate) Text on Verilog/SystemVerilog with Examples

    I am sure the internet is a good resource, but I am looking for books specifically. Besides Cilletti, there doesnt seem to be a lot of advanced verilog books with advanced HDL code examples in them.
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    [SOLVED] Good Advanced Level (Graduate) Text on Verilog/SystemVerilog with Examples

    I am looking for a Good Advanced Level (Graduate) Text on Verilog/SystemVerilog with Examples of Verilog Code - I know Cilletti is a good book : Advanced Digital Design with Verilog HDL - does anyone know of any others ?
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    IC Layout of RF Blocks

    I have a question about IC Layout and Grounding. In this IC layout below, I have 4 blocks, all connected to the same ground. When IC layout is done and chip is fabricated, the way the buffers are grounded (and their IC layout) caused the circuit to oscillate. In IC layout then would the...
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    Ditherless Digital PLL

    Why would you want a ditherless Digital PLL and why is it important ?
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    RF Layout Receiver

    I am doing analog layout of an LNA and Mixer. What would be the best way to approach the IC Layout of these two blocks - should they each have their own ground planes ? Also they should each have their own analog supply ? Any other issues with grounding I should be aware of ? Any other...

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