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Recent content by pruki1

  1. P

    sampling an slow freq timer after fast stobe - hard problem detailed below

    still all solutions submitted are not sufficient can you write a verilog model for it that has no cross domain clock problems ?
  2. P

    sampling an slow freq timer after fast stobe - hard problem detailed below

    ok, still suppose timer S runs at 100 Mhz (10ns) while clock X runs at 500 M (2ns) when there is a strobe X, application must get the timer value up to 4 X cycles (8 ns) thats less than S clock period so problem seems to be solved by sampling the timer every 10 ns at S domain but the transfer...
  3. P

    sampling an slow freq timer after fast stobe - hard problem detailed below

    i have a very hard problem there is a timer that is clocked by clock_S while someone sends a 1 cycle strobe at clock freq X need to supply a valid value of timer after maximum 4 X clocks from strobe cdc should be kept now if clock S is fast no problem, strobe X can be synced to domain Sand it...

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