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That is the question and they haven't given any transmission line length. I recently had an interview where they asked me the same type of question
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Your answer is right. Can you tell me how you got it
Hi,
I am going through interview questions online and I found this question. Can anyone give me an answer
Consider a transmission line with characteristic impedance Z?. This transmission line is terminated in Zo. The input impedance is
(A) 4 Z
(B) 2 Z
(C) Z
(D) Z /2
I am going through a paper on RF switches in SOS process.It is mentioned that compression is reached when Vds forces Vgs to rise above vth. |Vdspk|=2(vth-Vgs). Can anyone explain how this equation is obtained. At vds extremes, FET is temporarily on and passes current and clips the voltage...
I'm solving a problem in gray mayer Analysis and Design of Analog Integrated Circuits. The problem number is 3.20. I'm attaching the problem and solution in manual.
My question is, the problem should be approached as CC-CB amplifier instead of differential amplifier. But the manual has...
I have two antenna designs in hfss. I want to include one antenna into other antenna file (instantiate design in cadence). Is there any way to perform this function in hfss?
When we set the boundary in hfss, it computes maxwells equation on this boundary?. If so, the radiation pattern will be...
Hi,
I'm designing inductor model in CMOS process. I found few formulaes online for the model. The resistance for silicon substrate is given by
Rsi=resistivity *2/(w*l)
where w and l are width and length of the inductor. I'm getting the value around 36 Kohm. Is it right?
Hello,
I have designed a power amplifier in cadence virtuoso and generated gds file. Now I want to use that gds in ADS to find the mutual inductance across the inductors. I successfully extracted gds file using .map. However, when I'm performing EM simulations, I'm getting the following error...
Hello,
I have implemented three RF designs. Two of them work between 3.1 GHz and 6 GHz. One design works at 500 MHz. All of them are integrated in 1.5 mm X 1.5 mm chip. All of them share same supply and ground. What are the possible interference and noises that can occur in implementation...
Re: two amplifier ouputs connected to same load
Thank you for the details. For example, I'm using low power amplifiers that has output power of 4 dBm in CMOS 180 nm technology and I don't want to install external components such as power combiers and circulators at the output. Does this...
Re: two amplifier ouputs connected to same load
This is the first time I'm seeing this kind of architecture without power combiners. I'm doubtful to implement it in practice. Do u know any similar architecture as mentioned in the document (load sharing with amplifiers).
Thanks.
Re: two amplifier ouputs connected to same load
Thank you for the information. So, the performance degradation is interms of power dissipation and efficiency?
Re: two amplifier ouputs connected to same load
Hello,
I uploaded the document. Please let me know if you have any issues opening the document.
Thank you
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