Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Hi,
I have a doubt regarding electromigration on nets in VLSI design.
In any SoC design, there are only three nets: the Power/Ground net, Signal net, and Clock net.
My question is which of the net is more prone to electromigration and why?
Please correct me if my question or net assumptions...
vhdl doubt
how to add a text file into a vhdl desription...........if we r using verilog we can use 'include compiler directive to include a text file in to our description......is there any method in vhdl ......
verilog doubt
i use wand or wor type net to resolve strength contention for wire type net......but am unable to reslve strength contention for trireg type net........
verilog doubt
can any one help in finding out "strength contention resolution with trireg nets"
i know strength contention resolution using wire net.....but not able to find with trireg nets...
thanks
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
