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Yes, it may due to that not constrainted during synthesis or over constrained or it may be real violation which cant met.
Floorplan and macro placement will make timing worse, not better as synthesis assumes ideal net delay.
Re: uncomplete reset assignmet to reg, What happens in Synth
All FF's will have SET/RESET pin depend upon '1' or '0'. Since you say only 10'b... it will append zeros to MSB. So it will be reset for FF 12:10.
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