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hai,
Can any one help me out in knowing answer about BIST.
I need a small clarification as how BIST is tested or verified that the pattern generated by BIST is right/ correct.
for Eg.. we are testing a bench mark circuit so when it is tested in BIST it will generate a pattern or a chain if i...
Re: jpeg+fpga
dear vs 21 can i have code for that as i have completed my dct block in "fpga implementation of pipelined 2D-DCT and quantization architecture for JPEG image compression" in this project and it is so that i could not able to get code or source for designing quantizer and zigzager...
Re: fpga fir
dear amit can i know on what u have implemented and u hav seen on fpga can i get some info
as i need help on 2d dct implementation and in that i need quantizer and zigzager
---------- Post added at 18:28 ---------- Previous post was at 18:22 ----------
sir ur code is not seen...
"fpga implementation of pipelined 2D-DCT and quantization architecture for JPEG image
dear members can any one help me in implementing this project plssssssss
i had my 2d-dct block part completed and i need help in designing of quantizer and zigzager blocks in that or i request u to give me...
thank u avinash but my ambiguity is not cleared still
input is ok but how will it start to initialise and generate random pattern
shuld it generate on its own if so it should be having some driving factor to generate its pattern
2)will it need a power supply to generate pattern or any other...
thank u sir but my doubt was still not solved
can i know how would lfsr generate pseudo random pattern i know its operation but i dont know about seed of lfsr
mainly how will it be initiated to taking one by one pattern in it ,how wil it initialise to work actually do some power required as...
hai ramu gate level net list is readily available for some of the circuits directly kindly browse the site
and sending netlist is for around for all sequential is a bit difficult so kindly u browse it u vl surely get it there is no other alternative rather than to belive the net source wether...
can any one tell me what are possible inputs for a lfsr and a bist
as they will be producing output at a random sequence and test on its own respectively .
but what could be possible inputs for both lfsr and bist
hey ramu i vl giv u some clue as i know how v vl get that net list but my prob is that my halwa professors need circuit diagrams so can u also help me out
the site i would suggest u is WWW: ISCAS89 Sequential Benchmark Circuits
can u also kindly help me how to get circuit diagrams of...
request that any one can provide me circuits for bench mark circuit iwe do have the net list so i will be very thank ful if some one can help me out in providing site where i get circuits of iscas89 bench mark circuits or directly send me s 386 circuit diagram
can get circuit circuit diagram of any ISCA'S89 BENCH MARK CIRCIUTS for implementation of a testing project
as i m doing a project in power reduction in BIST so in order to test it i have got S27 circuit diagram with me so i need some kind heart to give circuit diagram of some other circuit...
hi
I am Prakaash pursuing my M.Tech and i took up a project regarding power reduction in bist
i know the concept and studied paper but its a basic problem is that i am not getting idea how to implement it
there r 2 methods to reduce power out of which
1)using bit swapping LFSR and...
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