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Hi,
Would like to raise the question again. What exactly is the difference between atpg library and verilog library??
I am looking for a generic level answer which will be easy to understand.
Thanks.
But why do you need functional vectors when you are doing DFT? All your fault models are very well capable of figuring out every faults in your design, then what is the need of your functional vectors to figure out manufacturing defects??
Hi guys,
Just for clarification.
1. STA has to be done on everything including the scan chains, otherwise there is no way you can close the path between the flops for timing. What I am trying to say is, when you are in SCAN_MODE, the path is from Q to SI of all flops in the chain. This path...
Hi guys,
Sorry for the late reply. Was little busy with my work.
Well, I hope you guys understand what logic cone is all about. With that assumption that you know about it, when logic cones become very big, the EC tool is not able to handle it and thus gives you aborts. In order to handle abort...
Generally there are 2 kinds of problem that you face when doing LEC. Aborts and Mismatches.
Aborts are when your logic cone is too huge, your tool will not be able to check for equivalency between the RTL/Netlist to Netlist. I mean, the tool will exhaust after certain amount of tries giving you...
Hi..
Any logic which is going to be a part of your chip needs to be synthesizable. Be it Scan Technique or your Bist everything is synthesizable. DFT is not written in RTL. We don't really code for DFT.
We insert the Scan Circuitry in an existing netlist. For Eg. We use a tool called DFTAdvisor...
Answering serially:
1. There is no point in generating patterns for RTL. DFT is done on a synthesized netlist and hence patterns need to be generated only on DFT inserted netlist. Moreover all the DFT tools take the netlist as an input not the RTL.
2. DFT circuitry means all your flops will be...
Hi All,
I am trying to understand the measure PO and measure SCO statement used in any ATPG Testproc file. My confusion is in the time plate defined below, the measure PO statement is being executed before the clocks are being pulsed. This doesn't make any sense to me because I am expecting...
Hi All,
I am trying to understand the measure PO and measure SCO statement used in any ATPG Testproc file. My confusion is in the time plate defined below, the measure PO statement is being executed before the clocks are being pulsed. This doesn't make any sense to me because I am expecting...
Hi,
Is there any particular document which explains lockup Latches with timing diagram and all the possible scenarios where it can be used???
Thanks for the help.
Hi All,
Just started doing C programming recently. I will be glad if anyone can help me out with my problem.
I have structure named PERSON. Inside this I have Name and Age.
I have another Structure called SCHOOL which has Location and Year.
Now I want to point to this struct called...
Dear All,
I have coded a small structure and initialized it. I am getting some error while compiling this code. How can I resolve this problem?? I will be grateful for your help.
C code:
struct ver_id
{
U32 address;
U32 mode_val;
U32 rst_val;
U32 majVer : 12;
struct regDef...
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