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hi
Thank you for your suggestion.
one more question is should i design LDO while load is connected or i should design with no load condition ?
if i should connect load then what should be load value ?
hi
thanks nitishn5
now i have design it again all the blocks together and simulate it. It is working with DC analysis fine with no load at output with 10nF capacitor.Power transistor is operating in saturation with Vds=75mV.(it is gpdk 90 nm Technology with Cadence Virtuoso)
But as soon as i...
Hi
I have Design Op-Amp working with 1.2V Supply Voltage.
Then i have connected power transistor and feedback resistors, But as soon as i connect output of feed back resistors to the input of Op-amp all biasing voltages get changes and op amp output decreases to around 200mV and power...
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