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hi, man.
i suggest you to search paper on:
PFC using buck-boost
and
LCC resonant converter.
the application note whitch publiced by IR,Fairchild,ST,Philips...
hope may do some .
pfc flyback
hi, dear
i have downloaded your paper.
i found it useful, but i can not understand ITALIA language.
Would you please translate it into english, and upload it .
This will hlep me a lot !
hope you happy everyday.:D
Hi ,FvM
Yes, I have done like that. i get the power every main component consumes. but the power consumed by inductor ,diode model can not reduce. so i think i can breach at this point.(POWER MOSFET )
Thank you ,for your attention!
dc dc converter mosfet
Hi ,guys
I simulate the efficiency of the boost converter ,and find that the POWER
MOSFET consume about 8 percent of the whole power. Does it large ? how
can i improve this? And how can i get the spec for the driver of the POWER
MOSFET. (such as delay time...
hi , i know in kujik band gap reference, the band gap generate part will be the
load of the op-amp. so i want to know how to do AC sweep of the op-amp in it.
waiting for your good ideas!
Re: question about how to reduce ground bounce (switching no
Thanks . but i can not understand clearly. Can you show me a example about that ?
Can any reference book i need to read?
thank you . i think you must be very good at design boost converter. and i have
some more questions.
the input voltage is 2.7v, output current is 20mA, output voltage is 8.2v.
the efficiency i want is 85%.
discrete inductor ? the inductor'esr now is 0.26ohm. does it big?
you have to be...
Re: question about how to reduce ground bounce (switching no
er, i have thought about that ,but i didnot know how many bonds can i parallel.
simply to me, i want to know how small the parasitic ESR and ESL can be ?
can you tell me ?
Added after 35 minutes:
Thank you !
i now give the...
i am now do my circuit simulation.it is a boost. And the efficiency is too low, about 75%.
and the rest power is occupied by :
inductor model : 6%
diode : 5.34%
power mosfet (a high voltage model): 8.18%
power line:3.5% (include power ,ground ,bondwire,package pararistic)
does the above...
bond wire inductance qfn ground
Recently, i simulate my circuit with package model, in which the digital ground and analog ground share the same pin GND. now, the problem came out, they
have impact on each other, in the end the circuit can not work correctly. how can i do ? can anyone help...
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