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Recent content by pforpashya

  1. pforpashya

    3 input xor gate implementation using static cmos

    here is the implemented circuit from a book but i am not able to understand how its implemented......can somebody explain to me ? this technique is used to save the number of transistors.
  2. pforpashya

    Fourier series for rectangular pulse function

    Use any signal processing book whose author is Oppenhiam
  3. pforpashya

    FinFET biasing IDS Vs Width

    Hi, I am trying to understand DC biasing in a paper having 2-stage LNA implemented using FinFET in 32nm. The width mentioned of first stage cascode is 1µm and second stage is 2.4µm. The DC currents are not mentioned but overall DC power is mentioned which is 12mW so, assuming 6mW in first...
  4. pforpashya

    cascode and self regulated circuit difference

    Whenever you add a cascode device, some of the voltage from supply voltage will drop across it and hence reducing overall voltage swings of the circuit and that is nothing but headroom.
  5. pforpashya

    Suggestion required to make gain positive and NF less than7.0dB

    well I have simulated the circuit And the maximum available gain is negative and noise figure is also high Any comments will be appreciated....
  6. pforpashya

    Suggestion required to make gain positive and NF less than7.0dB

    got Cgs around 40fF - - - Updated - - - I done DC analysis of MOSFET both CS and cascaded stage by giving VDS as 0.6V(half of 1.2 my VDD) but when I connect them as cascode stage how to get that 0.6 v in between of two MOSFET I think I have to play with VGS then but again all the values will...
  7. pforpashya

    Suggestion required to make gain positive and NF less than7.0dB

    ok So can you tell me how can I modify the above schematic?
  8. pforpashya

    Suggestion required to make gain positive and NF less than7.0dB

    I agree I am extremely noob in ADS and my aim really big.....but currently attending ADS paid session is not possible for me alone so my last attempt to get cgs is, ok I have attempted to get Cgs using following schematic, I hope its correct. Now in display window I am not able to set AC.vgs=1...
  9. pforpashya

    Suggestion required to make gain positive and NF less than7.0dB

    give me a min - - - Updated - - - Here is the schematic, is it correct? - - - Updated - - - OK. Thanks for your valuable time.
  10. pforpashya

    Suggestion required to make gain positive and NF less than7.0dB

    Sorry my bad I tried to take VAC source from sources frequency domain and placed it in series with DC VGS. Then I tried to change value of this AC source to AC_vgs=1 but it gives me error am I doing correctly?
  11. pforpashya

    Suggestion required to make gain positive and NF less than7.0dB

    ok I will make threads - - - Updated - - - ok. I actually didn't understood what you mean when you said following As I try to change the VAC of AC source it gives me error
  12. pforpashya

    Suggestion required to make gain positive and NF less than7.0dB

    Now I have increased VDD to 1.8V this is VG of MOSFET 1 Voltage between MOSFET 1 and MOSFET 2 is 1.08 so Vgs of MOSFET 1 is 0.72v which is approx. same as VGs of MOSFET 2 Now drain current has increased to 8.48mA due to all this how to compensate this current - - - Updated - - - Yeah...
  13. pforpashya

    Suggestion required to make gain positive and NF less than7.0dB

    thanks for the links really appreciate it as I am new to this domain and also to ADS
  14. pforpashya

    Suggestion required to make gain positive and NF less than7.0dB

    yeah. thanks for your comment . I will redesign it again. come to know my mistake can I send you a friend request? one last question is width of MOSFET is higher i.e. 20um at 60ghz? so that next time I will go with lesser width
  15. pforpashya

    Suggestion required to make gain positive and NF less than7.0dB

    Hi, I am attaching dc-analysis image - - - Updated - - - and here is circuit

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