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Hi I am using Cadence pnoise for VCO (ring) simulation.
Why my pnoise is greather than 0 dBc as the offset is close to 0?
It is also 60 dBc at 1 Hz. Is it correct??
Hi I personally prefer PA design in ADS. But most of the CMOS foundry are only available in Cadence.
Is it equally capable to use Cadence for PA design? I am only talking about schematic design, not layout.
Did you trust the foundry's spectre model, or you develop your own model?
As titled, each time after simulation, I need to change the line color, size and add equation in wavescan. It takes time and is very inefficient.
I am using IC 5.X and pls kindly help me on this.
Thank you very much.
Hi I don't know why the Cadence environment is configured in this way, but it is very inconvenient. The symptom is:
Why i click any instance in cadence schematic, it is added to the selection. If you keep clicking, all the resistor, cap and transistors are selected.
To de-select, I have to...
What is M3x and M4x for exactly? It seems to be able to increase the bandwidth. But how?
Normally cross coupling is used in common source. why in this topology?
Thanks a million times for your answer!!
what is the material of MMIC chip carrier?
anyone knows where to get it??
i intend to wire bond the mmic chip to PCB board following the schematic shown in the attachment.
Hi i m simulating a cpw antenna, as you have discussed a lot in other threads.
could anyone kindly tell me what's wrong with my port setup? it's working from 0.5ghz to 2.5 ghz.
i use waveport in the design, following the rule of 3*(2g+w) by 4*h, i still dont get the right results.
or could...
gcpw in hfss
a lot of thanks
Added after 4 hours 13 minutes:
can someone share a project file for this setup?
your noble deeds could benefit a lot of guys who are not familiar with HFSS.
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