Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Recent content by pejotr

  1. P

    strange behaviour of state machine in vhdl

    In the following code, which is well known 2 process state machine, if i comment line "if rising_edge(CK) then", corresponding "end if" and remove CK from sensitivity listi of e0 process it produces some strange results, why ? library ieee; use ieee.numeric_std.all; use...

Part and Inventory Search

Back
Top