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Recent content by peekpeek

  1. P

    Chip voltage and temperature variation

    The COD is batter then the QFN package. It have 20mV lower than the QFN for both DVDD and DVDD_RAM. Does this means It is IR Drop problem? Can there any experiment I can do?
  2. P

    Chip voltage and temperature variation

    I have lower the chip DVDD LDO to 0.7mv. I provide the digital supply from the DVDD PIN so I could adjust the voltage from the external supply. What I said 1.0v and 0.99v is provide from the external supply. The abnormal I means CPU run out of control. Because I am digital engineer, I care about...
  3. P

    Chip voltage and temperature variation

    Could you please tell me how to design a test to prove it?
  4. P

    Chip voltage and temperature variation

    Hi Our chip has passed the ss corner 0.99v -40c and ff corner 1.21v 125c at PT STA sign off. I expected the chip can work lower than 0.99v because it is tt coner and 25c degree. But when the chip comming back, It can only work at as low as 1.0v. The interesting thing is, temperature...
  5. P

    quartus use dc gtech netlist

    Hi, Does anybody know how to let the Quartus read DC generated gtech netlist? Quartus can't map GTECH_xxx cells. Thanks!
  6. P

    lec check abort point help

    Thank you for your advice. stevepre
  7. P

    lec check abort point help

    conformal abort I think as stevepre said is right. I have a adder sharing. When I remove the adder the lec do not have any abort point. Can anybody tell me if I want keep the adder how can I do with the lec. Thanks!
  8. P

    lec check abort point help

    lec multiplier check I don't have the conformal ultra license. SO if I want to clear must I change the rtl? Can you give me some advise?
  9. P

    lec check abort point help

    lec multiplier Now I use conformal to check the rtl and gate. The gate is synthesis by dc. But the conformal report some abort point. How to handle these abort points? How to make them equivelent? Can anybody help me!! Thanks!
  10. P

    A problem in Using DW component

    I allso meet the same problem.
  11. P

    Which language is more popular, Verilog or VHDL?

    Re: About Verilog and VHDL? verilog is more popular

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