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Recent content by pcca

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    Post-layout simulation of sigma-delta modulators "error"

    Hello, I am designing a low-voltage SD modulator and I am having some troubles in post-layout simulation. I have performed the layout extraction with assura (RC - decoupled capacitances) and during the simulation (spectre with APS++ in conservative mode), the output DC level of the third...
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    Hspice not able to output tr0 files properly ? can't see the waveform

    Hi, Try to use the following in your code: .OPTION POST=1 and use .PROBE(*) for testing purpose only. Also, try to open your .st0 file with waveviewer (wv at terminal) . Regards.
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    Hspice Monte Carlo - Save data with veriloA script

    Thank you dick_freebird. I read your example and found the meaning of % I,% C, etc (listed below). % C Design filename % D Date (yy-mm-dd) % H Host name % S Simulator type % P Unix process ID % T Time (24hh: mm: ss) % I Instance name % A Analysis name However, I was not able to use a variable...
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    Hspice Monte Carlo - Save data with veriloA script

    Hello, I am trying to perform some monte carlo runs in an low-voltage delta-sigma modulador using Hspice. A verilogA script is used to save the output bitstream data in a txt file, for example 'bitstream.txt'. I would like to know if it is possible to run monte carlo and save each monte carlo...
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    1.8V to 1.2V clock signal for ADC testing purposes

    Hi Brian, I agree with you. But, I will perform some tests using spice simulation at least. I'll let you know about the solution and this results. Regards, PCCA.
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    1.8V to 1.2V clock signal for ADC testing purposes

    Hi Klaus, They are custom designed delta-sigma modulators in 130 nm CMOS process (1.2V is the typical power supply). The 0.6V clock signal is for a low-voltage modulator, also custom designed. Our lab is quite new and we do not have a good clock generator yet. I appreciate your attention.
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    1.8V to 1.2V clock signal for ADC testing purposes

    Thanks Brian, I will think about this solution. The clock frequencies are: 125MHz@1.2V and 10MHz@0.6V. I will simulate some diodes to see their impact at frequencies up to 100 MHz. Kind regards.
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    1.8V to 1.2V clock signal for ADC testing purposes

    Hello, I need to test some delta sigma modulators. I would like to ask how to convert a 1.8V single-ended clock to a 1.2V and 0.6V single-ended clock (on a PCB board). Is it possible? If it is not possible, may your suggest a low-cost clock evaluation board with output clocks of 1.2V and 0.6V...
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    Telescopic OTA DC Gain in 130 nm

    Thanks everybody for the replies! and sorry for reply this just now. I have to change my high level design and know I am working on it again. As JGK said, I need do define correctly my output swing before to define the OTA topology. Since folded cascode OTA presents higher power consumption it...
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    Why I cannot use cadence calculator to plot waveform

    Hello, You need to plot both waves (input and output). A simple and fast solution: select an wave (vout for example), click with the mouse right button and select calculator. The variable related with this wave is displayed. Copy this information. After that select on the wavevier the Vin...
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    Definition of wideband sigma-delta modulatores

    Hello, There is a specific definition for wideband sigma-delta modulators? What are the bandiwidth range in this case? Regards, PCCA.
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    Telescopic OTA DC Gain in 130 nm

    Thanks for the reply, JGK. Don't worry about the ""homework" of the power dissipassion calculation or even the use of minimum channel length transistors =). I just created the topic to have an overview about the possibilites of this design and "get a sense" of the power dissipation from...
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    Telescopic OTA DC Gain in 130 nm

    Hello, I need to design an OTA in 0.13 µm CMOS (1.2 V) technology. My specs are: Av=80 db GBW>250 MHz. Slew rate > 100v/µs It is possible with a single telescopic stage to achieve this results? Any idea about the power need for achieve this specs? Regards
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    Continuous-time Sigma Delta Design

    Hello, thikgaidep. In fact, I did not read the paper you cited. At this moment I am performing some simulations to evaluate clock jitter influence in CT SD modulators. I am simulating modulators with NRZ and SCR DACs in Simulink. To design my CT modulators I start with the sigma-delta toolbox...
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    Continuous-time Sigma Delta Design

    Hello, thikgaidep I am starting to work with CT Sigma-Delta in my master dissertation. Well, I studied both techniques, and I prefer the first one. It has more documentation, and a lot of papers dealing with. Also, you can compare the responses of th DT loop and the CT after transformation. A...
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