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Altough I cannot say exactly where the latch is located looking at your code, I think you just have too much logic inside always(*) block.
When you have this much assincronous logic (and lots of case inside the block), latches happens almost naturally. I think that, in general, designers should...
Similarly to BRAM, you have two choices:
Instantiate via primitive/IP, and configure your DSP ports, pipelines and functions manually.
Instantiate via code/templates, and let the tool to instantiate the DSP for you.
Instantiating via IP is a bit more complicating than BRAM, you have to read...
You connect LEDs to INIT_B and DONE if you want LED signalling showing you FPGA is loaded (DONE) and out of reset (INIT_B). It is very helpful for debugging. If you do not want any visual indication, the LEDs can be avoided.
I personally connect a LED on DONE, but do not use LED on INIT_B.
Have you tried to use some alternative simulator to perform this task?
If you only need a console output of the simulation, maybe you should try something as Icarus Verilog or Verilator, they are much faster than ModelSim. But you might need to somehow adapt your code.
You seem to have a good hardware background, which is good for FPGA design, and will help to avoid coding FPGA as software.
The first basic thing is to decide which hardware description language you want to follow. The most common are System Verilog and VHDL, but there are others. I recommend...
You can implement a flash dump, and read from a seleted address range. Optionally, you can make some kind of script which dump the flash in a infinite loop, for example.
For writing tests, you can write into a unused sector, and limit your tests to writing and erasing this sector. Again, loop...
Thanks for the Reply FvM. That´s my understanding as well.
Vivado behavioral simulation is not very verbose in this case, there is no other simulation info/warning/error message which can help me here. I tried to increase the verbosity, without success.
Well, I discovered that, while behavioral simulation does not work, simulation based on synthesis does. So I am working with this for now. Hopefully, looking at synthesis simulation, I can discover what is going on.
Hello All,
I am trying to connect a complete cache (L1D + L1I + L2 + DDR3 Controller) into my custom core. Because I really need to understand the connections and logic behind it - I want to customize also the cache at some level in the future - I am connecting these IP blocks manually.
I am...
Contact a direct Xilinx representative and ask for an official quotation instead buying directly from Digikey or other distibuters. Depending of your volume, application and required delivery time, you may have a pleasant surprise. But if you are looking to buy few components for prototyping...
Hello mtaciano ,
Some comments:
I suggest to remove the division in the earlier implementations (just comment the division operation in ULA.v). This should make your life easier and faster for now. Division is a very costly operation and demands a lot of logic. Doing this in a one-cycle...
He is correct here. You cannot do this because when you include a file twice, the tool will read the file twice and will detect duplicate registers/wires/parameters/(other definition I might have forgotten).
Note, however, that there are ways to workaround this. You can, for example do the...
I am not totally sure what exacts formats Vivado accepts or deny, but I always use <ENTER> as a separation of BRAM words. Also, I think BRAM expects a fixed length value.
So, in you file "out_i.txt" you have (first 8 words):
fe63 fee8 ff73 0 8d 118 19d 21b
I would put this as
fe63
fee8
ff73...
Ok, first of all, your problem is that your memory is filled with zeros in simulation or in the FPGA? Is it a simulation problem or a synthesis problem?
For both cases you probably get a meaningful message in the log, giving a hint of why the memory could not be initialized. Please note you...
You are still thinking serially, as if you are programming a sequential language. So, you expect that the for loop and thinks that happens inside the for loop happens sequentially; on hardware description language it does not happen.
First thing is that one FPGA is a logic device, which...
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