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Recent content by paviljonac

  1. P

    implementation if OFDM with FPGA

    www.journal.tfc.kg.ac.yu/Vol_1-3/14-Dramicanin.pdf
  2. P

    big fine ball grid footprints needed! (orcad)

    hi there, i need ff1152 and fg456 footprints for orcad for virtex2 chip range. if someone has to share them with me, i'm ready to give interesting xilinx IP core rewards, or if someone has a problems with sysgen i could help with fixing. greetings
  3. P

    xilinx FPGA Virtex II XC2V6000

    i didn't have problems of that kind with any of the fpgas i've been using so far
  4. P

    need help with designing QPSK modulator/demodulator

    hi please look at this. this is v22_bis old simple qam modem design. it has all the basics you need to enter the field of modem design: 1. polyphase shaping filter with upsampling 2. mixer 3. another upsampling 4. dac/adc + channel effects emulation 5. AGC with hilbert transform anvelope...
  5. P

    Opinions on performance of Virtex-4 FPGA

    Virtex-4 when i recall all bad memories on suspicious behaviour of big v2 chips with foundation 5... i will let v4 to age a little bit.
  6. P

    implement a DSP algorithm in a FPGA

    cordic is very suitable algorithm for sin/cos generator, and i use it very often in my design practice.
  7. P

    Do you guys really use the function & Procedure in VHDL?

    i use vhdl for fpga design. i don't use neither functions nor procedures.
  8. P

    Drive and Slew Rate for SDRAM and other devices??

    slew rate + drive strength hi, fast slew rate is not ALWAYS better than slow slew rate. fast transitions can cause undesired reflection. on the other hand, by limiting drive strength one can avoid ground bouncing. this issue is critical when rating buses.
  9. P

    Using 802.11a MAC in a FPGA?

    btw, i've been developing 802.11a digital PHY for intermediate frequency range (software defined radio). for example, demodulator with smoothed LS channel estimation/equalizing, full featured synchronization acquisition and tracking, and FEC, fits into virtex2 2000.
  10. P

    How to program a VHDL to implement demodulation of AM, FM, P

    most intuitive tool for designing digital communication on FPGA (to be more specific: for DSP in digital communication) is Xilinx System Generator. It generates VHDL according to the model defined in Simulink. Also, the question of theoretical background (what exactly to implement) is more...
  11. P

    How to Interface FPGA with DSP(TEXAS)

    using TMS320C5510 and virtex2. you can interface thru EMIF of dsp, where FPGA is configured to be seen as static memory space, or thru McBSP serially if suitable.
  12. P

    How to implement a specific MCU/CPU in FPGAs?

    i presume you want to try something for free. there is a lot of junk outhere on net, but i've tried PIC from opencores; it works just fine.
  13. P

    Are there some tools help one to write testbench(vhdl)?

    Xilinx System Generator for simulink can generate vhdl test benches.
  14. P

    Is it better to use DSP or FPGA ?

    Re: DSP or FPGA there is a trend to use so called "soft processor cores" lately. these are optimized FPGA cores, used for decision-oriented tasks within system on reconfigurable chip... as i know, DSP cores in the terms of rough definition of DSPs as "CPU with multiplier"... are not available!?
  15. P

    How can ISE communicate with Matlab ?

    Re: ISE and Matlab ? there is no need to change auto-generated code. but, sometimes there is a need to use project generated in sysgen as a module in bigger design (which for example employ multiple clock domains...)... only if so, you should change some of the autogenerated files.
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