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yes I check. There is no current through M1. M1 is not conducting.
And I got it. R6 is charging C1 from Q5 base. It means to charge the C1 we don't need PMOS anymore.
Thanks.😊
Hi all,
I have this PMOS circuit and would like to figure out this working.
I would like to know why the M1 is working while the Q5 is always on. As Q5 is always on, it will pull the source to Gate which should turn off the PMOS.
Am I getting this in the wrong way or something else?
Thanks.
Hi all,
I have this below circuit and I would like to work it as a comparator circuit.
For M1 and q1 it is working as expected. while for M2 it is not. My expectation from IR7 is more than 3A. How could I achieve it?
thanks.
In the below image, I would like to make the current profile.
Theoritically I have to add some comparators in the control loop. Threshold for the comparators will be set based on the vds. For the moment, one is free to opt threshold voltage. (later I will modify it for particular vds voltage)...
cost effective
1653983076
Thanks for the information. I have done my simulation with PMOS circuit and it's worked as per requirement. But i would like to make simulation with NMOS for comparision purpose. I would like to draw some comments on both circuitary. SO I am more intended to work with...
To keep within the SOA region of NMOS. As per the SOA, at high voltage we need less current so what i am looking is continuous current steps.
the idea behind is like initially some current that will charge up the cap, then some more current will come then it will charge the cap and then final...
@FvM
you have done right simulation that also I have done.
But results are not expected. Vout should be reached till 42V. you can choose another opamp that work with 3,3V. expected result is something like (posted in post 10).
control loop is made to increase the gain.
@crutschow
Thanks for this but same phenomena I would like to achieve with NMOS(M1). There you can use an opamp for gate control and npn for fast discharge.
So any suggestion?
that schematic..
1653651157
Cap will charge upto 42V.
1653653263
Cap will charge upto 42V.
so first I don't have choice to use LM317 voltage regulator. And I am charging the cap to the supply voltage. while in your simulation cap will be charged upto 3V, while supply is 12v. That's not my...
SO can you give a modified scatch?
1653648562
Okah so for a while see the circuit like this. (attached).
Now you can see I need 700mV at the base of NPN but I am using a current sense resistor R1 that is 2mohm and let's suppose maximum current is 1A then we have only 2mV but this can not turn...
HI all,
I have this below mentioned circuit. Here I would like to charge the capacitor but in steps. And these steps will be based on the Vds of MOSFET.(it can be seen in the second image).
I have a shunt resistor (R1) either 1mohm or 2 mohm. So to turn on the NPN, I need atleast 700mV so using...
Well, LTspice consider it as the additional capacitor.
it will help the more linear transition of VDS. As if the capacitor is large enough, it will take more time to discharge and VDS will fall down slowly.
V(S,G) is gate to source voltage of PMOS.
(Kindly have a look in the below images)
I...
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