Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Dear community,
I try to design a delta-sigma modulator. I have fully differential structure and the amplifier is simple folded cascode opamp w/ nMOS input devices. When I implement a sole switched cap integrator out of these, everything works very well. However, when I modify the structure...
No it's clear, I didn't know that we can do that indeed. Well, after a successful simulation for 50ms, when I say direct plot, it does plot only until the time instance it gets stuck, i.e. until 18ms for above figure but not until 50ms. When I import this data to Matlab, I see this figure. The...
Assuming a symmetric supply (i.e. VSS = - VDD), the half supply range is used as the Vref and -Vref (i.e. Vref = VDD/2 = |VSS|/2). The input amplitude is also limited to the same range. In fact, the sum of Vref and Vin is maximum 0.8 x VDD/2
What exactly do you mean by resetting the output...
Dear community,
I have designed a 1st order 1-bit delta-sigma modulator. I have implemented the fully differential architecture proposed on p31 of Schreier's "Understanding Delta-Sigma Data Converters" book. After running the simulation in Cadence, I import the data into Matlab to process it...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
