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Recent content by owen_li

  1. O

    How to determine slew trip point

    Yeah. we usually use 30-70 as the trip measure points to characterize the slew number in timing library. But I do not know why select such pair of points to model the transtion time. Thanks!
  2. O

    How to determine slew trip point

    Hi As we know, in deep sub-micron design, we usually model the slew ( transition time) between the trip points 30% to 70%. It is said that it will lost some accuracy when using the trip points fro 10% to 90%. Could you tell the cause why using the trip points from 30% to 70% ？ Is there any...
  3. O

    [SOLVED] capture path across clock domain in DFT mode

    Good explanation. Thanks Maulin & harpv
  4. O

    [SOLVED] capture path across clock domain in DFT mode

    Thanks harpv. I think you are correct. I found some material on google about this topic. It said that ATPG will generate multiple test patterns and will let one clock domain toggle the capture clock. I want to want to find some DFT experts to confirm it. If there are many clock domain crossing...
  5. O

    [SOLVED] capture path across clock domain in DFT mode

    Hi artmalik I think you may misundertood my question. What I mean is the cross clock domain path on the capture path. Yes, if this isssue occurs on scan path, we can insert lockup latch to fix the hold violation. But what shall we do on the crossclock domain capture path...
  6. O

    [SOLVED] capture path across clock domain in DFT mode

    Hi, artmalik Thanks for your reply. I know the hold timing in functional mode can be ignored. My concern is the cross domain path in DFT mode. Coz the clocks will be synchronous in DFT mode, and the result of the capture path will be shift out cycle by cycle. So the hold timing...
  7. O

    [SOLVED] capture path across clock domain in DFT mode

    Hi. I just had a question about the cross clock domain capture issue in DFT. As we know, we can insert a lockup latch on the scan chain who is crossing the clock domain, to ease the hold timing fix. But how to hanle the capture path which is asynchronous from clock domain A to clock...
  8. O

    IC design service offering

    Hi. Our company is offering IC design service (including DFT and P&R). We have more than 20 engineers, average owning more than 6years' backend experience. Either Turn key or onSite design service can be provided. You can visit our website here: http://www.chipsea-design.com...
  9. O

    Why set hold uncertainy value in Signoff timing run

    Hi . When I run the find timing signoff, I found there are hold uncertainty set in SDC. As we know, jitter will not affect hold check. So why add such hold uncertainty ? what does it account for ? Thanks !
  10. O

    Recruite some digital P&R engineers in China

    Hi all. We want to find some digital P&R engineers in China. The package will be much better than most of the IC companies. If you are interested in this Job, plz contact me. Email is here: dream_hunter_1984@163.com Thanks!
  11. O

    How to do formal check after clock gate clone ?

    Hi. Coz I need to some stubborn clock gating setup violation, I made some clock gating cell clone. My question is how to do formak check then. Is there extra setting needed to be set in formal tool ? thanks!
  12. O

    where latches are used in ASIC design ?

    Yeah. In this case, hold violation is very huge. So If I tried to fix the hold, I should insert so many delay cells. Coz delay cells will have much variation between ss corner and ff corner, so setup check will fail. Using latch instead of delay cells will bring less variation, then hold...
  13. O

    where latches are used in ASIC design ?

    latches are not only just used to fix hold for scan chain, but also in some function cases. In my previous project, the hold violation is very hard to fix because of the setup and hold violation conflict. Delay cell has so much difference in delay under ss and ff corners. So we used the latch...
  14. O

    Why do we need to close timing with different voltage ?

    Hi Rahul I think closing timing under different voltage has something to do with the IR drop in the chip. As we know, the acctual voltage level on leaf cell in chip will have some swing (may be larger or smaller), comparing with the voltage applying to the power bump. coz, there will...
  15. O

    Formal verfication of DFT between placed netlist and synthesis netlist

    Thanks for your reply, rca. Do you mean ATPG simulation is the only way to check whether the scan structure is corrupted by PNR tools ? Another case is about the maximum scan register number in a signle scan chain. Is it the ATPG simulation only way to guarantee it after PNR implementation ...
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