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Recent content by onta00

  1. O

    Multi-vth design not performed

    The fact is I have no scenarios set
  2. O

    Multi-vth design not performed

    yes i used set_leakage_optimization true, but the result is the same
  3. O

    Multi-vth design not performed

    I’m trying to implement my design using two libraries, one containing cells with low threshold voltage, and the other one with high threshold voltage, in order to minimize the leakage power. I included them in the link library and target library, but at the end of the process, design compiler...
  4. O

    Critical Path in a design

    The command report_timing reports timing paths. I've used the same command in the top level entity and in the inner entity
  5. O

    Critical Path in a design

    Hi everyone After the compilation, given that we are at the top level, using the report_timing we obtain a certain path with a certain time X. After changing the current design(going more inside) and using the report_timing command again, we obtain a path with a time that is HIGHER than X. Why...
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