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Recent content by onlymusic16

  1. O

    Synopsys tool for milkyway database

    Most probably Astro
  2. O

    How does drive strength effect delay?

    Rightly said. When you start increasing, delay will only get decreased upto a certain extent and after that it will start increasing as the input cap also increases with increasing the size of the transistors. There is a good book by Ivans Sutherland which talks of this and much more. Go...
  3. O

    How to simulate 45nm and 65nm together in Hspice.

    I am not sure if hspice can take up two technology models at a time. But it is a very good problem. I will try to find out and get back if i find anything. But there are workarounds for everything:-)
  4. O

    cell_rise and rise_transition

    it means your cell's output delay is lesser than its transition time. This may be because of poor sizing at the final stage of your cell. Improve it otherwise if this cell has a large fanout, it will not be able to drive properly.
  5. O

    Why vil and vih has to be calculated through dc sweep ??

    Thank you from the core of my heart! I must say it was a clear cut explanation. It helped me a lot in finding Vil/Vih values of the receiver circuit. For Vol/Voh, i was able to understand the method but i do not understand why we attach a current source at output for finding Vol/Voh? best regards
  6. O

    Why vil and vih has to be calculated through dc sweep ??

    Hi Metalord, I am new in the i/o analog circuit domain. I am trying to calculate Vih/Vil & Voh/Vol values of receiver circuit. Since receiver was a bigger circuit, i decided to find out these values for a buffer first. I dc sweeped input from 0 to 1 and plotted output. Now what to do? How to...
  7. O

    why clock bufer contain fall and rise equal but normalbuffe

    Re: why clock bufer contain fall and rise equal but normalb Hint: Why clock signals are routed first than the normal data signals? What is so special abot clock signals?
  8. O

    to increase the speed of Design

    You can always design a dual edge triggered flip flop but you do not normally find them in your designs. Why? because very few EDA tools support them.
  9. O

    negative propagation delay buffer

    I agree with arun_prabhu.. Yes it can be achieved. The cons is that your inverter/buffer will be skewed(p/n would not be ~2:1) hence poor noise margin. Proper SI analysis should be done in that case.
  10. O

    Calibre extraction memory issue

    After doing LVS, do a back annotation and then try to extract. Without the back-annotation, extractor will not know which nets to extract. Also for doing lvs, you need to use extraction lvs deck file and not the regular lvs deck file. Please feel free to ask any questions!
  11. O

    Creating a Reference Library for Astro

    how to create a reference library Just check the Milkyway flow in the documentation. Once you are aware what it does, you can go through Astro Recommended Methodology(ARMD) flow.
  12. O

    Questions about using CeltIC tool

    celtic make_cdb ram Yes, its possible. Celtic NDC Si aware delay calculator can do that stuff. I am putting up a small doc which shows the flow. You can go through the detailed documentation available on sourcelink. Feel free to ask for any doubts. best regards.
  13. O

    Questions about using CeltIC tool

    celtic timing lib Transistor -> Gate -> Logic Block. By hierarchy, i mean one level up the design from transistors to Gates. For a circuit designer, the basic element is a transitor but a PnR designer will have a gate as the basic element. He should not be worried about the transistors...
  14. O

    Differnce between Hvt and Lvt cells

    svt and lvt cells difference If you want to see the difference, you should open the layout. You will see a mask layer difference.
  15. O

    Questions about using CeltIC tool

    what is cdb in noise analysis My two cents... As a circuit designer, i only have transistors as the basic elements. When i build gates, i use spice models to see the behaviour of the transistors(spice models correctly model the behaviour of the mosfets). But when someone takes your designed...
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