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I am designing a Folded Cascode OTA using TSMC 0.18u process in Cadence. After layout, I observed that the threshold voltage of the NMOS transistors in cascode increases by 40mV. I have connected the body terminals to ground. There is no significant change in the threshold voltages of the PMOS...
Hi Klaus,
Thanks for your help.
I tried using "((1*2)+(15*16))".
But I still faced problems. I have a Voltage regulator IC on the top layer. Now I want to route the Vout of the voltage regulator from the 15th Layer to an IC pin which is placed on the Top Layer. How can I solve this problem?
I...
Hello,
I am making a 4 layered RF Board. I have planned to have the following 4 layers
1. RF Lines
2. GND
15. POWER
16. Digital
All the components are on the Top Layer.
I am trying to use the Layer setting in Design Rules so that I can have vias from (1 to 2), (1 to 15), (1 to 16), (2 to 16)...
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