Increase in NMOS Threshold Voltage in Post-layout TSMC 0.18u process

[omkolhe]

I am designing a Folded Cascode OTA using TSMC 0.18u process in Cadence. After layout, I observed that the threshold voltage of the NMOS transistors in cascode increases by 40mV. I have connected the body terminals to ground. There is no significant change in the threshold voltages of the PMOS transistors used in the circuit. What could be the reason for the increase in the threshold voltage?

I have also tried just simulating a single NMOS transistor and observed the same increase in threshold voltage. I am using nmos3v transistors.

Thank you,
Om Kolhe

 

[dick_freebird]

Cascoding relieves drain voltage, and so will reduce DIBL
which is a "feature" of most short channel FETs.

NMOS and PMOS FETs in the same process often exhibit
different degrees of sensitivity to field and charging (HCE,
NBTI/PBTI) effects. For example NMOS tends to "walk in"
breakdown and leakage, at high drain fields while PMOS
"walks out" (breakdown up, leakage down). So don't read
too much into that aspect, it's gonna happen.

 

[Dominik Przyborowski]

WPE, LOD
Compare netlist of this transistor for pre and post layout

 

[dick_freebird]

A sophisticated PDK might also be imposing a model
of "proximity effects" post-layout, and a cascode
structure puts another transistor close by. I know
nothing about TSMC kits, particularly, to say whether
this is part of it.

 

[timof]

I doubt that 0.18 um technology would have complex layout-dependent effects (well proximity effect, length of diffusion, etc.) included into transistor SPICE models.

I would suggest to check the netlisting of the transistors (schematic netlist vs post-layout netlist - instance parameters, etc.) ), and also - operating conditions (applied coltages, temperature, etc.) - to make sure you are doing apples-to-apples comparison.