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hi
i am using simulink to generate c code from it for implementation on dsk6713 board. i have generated the code but when i saw it i did not find where input and output signals are? can any one help me how input and out signals are defined in simulink and then assigned for dsk6713 ,
thanks in...
standard exception: xnetlistengine:
hi
i need urgent help
i am generating bitstream from system generator for dsp but i got following error
Error 0001:
Reported by:
Unspecified
Details:
standard exception: XNetlistEngine:
An exception was raised...
pack:679 - unable to obey design constraints
hi i am new to fpga and ia m using system generator for dsp to generate vhdl code but during synthesizing i got this error
can any one help me
RROR:Pack:679 - Unable to obey design constraints...
what is explicit time period in dds v5
hi
i am new to system generator for dsp . i want to generate a 30 mhz signal from dds v5 block but i was unable to understand the parameters like explicit time period and output frequency array ialso read the help but in vain .can any one give me...
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