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RROR:Pack:679 - Unable to obey design constraints

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omair50

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pack:679 - unable to obey design constraints

hi i am new to fpga and ia m using system generator for dsp to generate vhdl code but during synthesizing i got this error
can any one help me

RROR:pack:679 - Unable to obey design constraints
(MACRONAME=Top_l/CustomLogic_l/u_sysgen_wrapper/U_sysgen/sysgen_dut/fpga_x0/d
ds_v5_0/comp0.core_instance0/hset, RLOC=X8Y1) which require the combination
of the following symbols into a single SLICE component:
FLOP symbol
"Top_l/CustomLogic_l/u_sysgen_wrapper/U_sysgen/sysgen_dut/fpga_x0/dds_v5_0/co
mp0.core_instance0/BU331" (Output Signal =
Top_l/CustomLogic_l/u_sysgen_wrapper/U_sysgen/sysgen_dut/fpga_x0/dds_v5_0/com
p0.core_instance0/N1146)
FLOP symbol
"Top_l/CustomLogic_l/u_sysgen_wrapper/U_sysgen/sysgen_dut/fpga_x0/dds_v5_0/co
mp0.core_instance0/BU333" (Output Signal =
Top_l/CustomLogic_l/u_sysgen_wrapper/U_sysgen/sysgen_dut/fpga_x0/dds_v5_0/com
p0.core_instance0/N1152)
LUT symbol
"Top_l/CustomLogic_l/u_sysgen_wrapper/U_sysgen/sysgen_dut/fpga_x0/dds_v5_0/co
mp0.core_instance0/BU531" (Output Signal =
Top_l/CustomLogic_l/u_sysgen_wrapper/U_sysgen/sysgen_dut/fpga_x0/dds_v5_0/com
p0.core_instance0/N2627)
MULTAND symbol
"Top_l/CustomLogic_l/u_sysgen_wrapper/U_sysgen/sysgen_dut/fpga_x0/dds_v5_0/co
mp0.core_instance0/BU532" (Output Signal =
Top_l/CustomLogic_l/u_sysgen_wrapper/U_sysgen/sysgen_dut/fpga_x0/dds_v5_0/com
p0.core_instance0/N2629)
MUXCY symbol
"Top_l/CustomLogic_l/u_sysgen_wrapper/U_sysgen/sysgen_dut/fpga_x0/dds_v5_0/co
mp0.core_instance0/BU533" (Output Signal =
Top_l/CustomLogic_l/u_sysgen_wrapper/U_sysgen/sysgen_dut/fpga_x0/dds_v5_0/com
p0.core_instance0/N2630)
XORCY symbol
"Top_l/CustomLogic_l/u_sysgen_wrapper/U_sysgen/sysgen_dut/fpga_x0/dds_v5_0/co
mp0.core_instance0/BU534" (Output Signal =
Top_l/CustomLogic_l/u_sysgen_wrapper/U_sysgen/sysgen_dut/fpga_x0/dds_v5_0/com
p0.core_instance0/N2464)
LUT symbol
"Top_l/CustomLogic_l/u_sysgen_wrapper/U_sysgen/sysgen_dut/fpga_x0/dds_v5_0/co
mp0.core_instance0/BU526" (Output Signal =
Top_l/CustomLogic_l/u_sysgen_wrapper/U_sysgen/sysgen_dut/fpga_x0/dds_v5_0/com
p0.core_instance0/N2622)
MULTAND symbol
"Top_l/CustomLogic_l/u_sysgen_wrapper/U_sysgen/sysgen_dut/fpga_x0/dds_v5_0/co
mp0.core_instance0/BU527" (Output Signal =
Top_l/CustomLogic_l/u_sysgen_wrapper/U_sysgen/sysgen_dut/fpga_x0/dds_v5_0/com
p0.core_instance0/N2624)
MUXCY symbol
"Top_l/CustomLogic_l/u_sysgen_wrapper/U_sysgen/sysgen_dut/fpga_x0/dds_v5_0/co
mp0.core_instance0/BU528" (Output Signal =
Top_l/CustomLogic_l/u_sysgen_wrapper/U_sysgen/sysgen_dut/fpga_x0/dds_v5_0/com
p0.core_instance0/N2625)
XORCY symbol
"Top_l/CustomLogic_l/u_sysgen_wrapper/U_sysgen/sysgen_dut/fpga_x0/dds_v5_0/co
mp0.core_instance0/BU529" (Output Signal =
Top_l/CustomLogic_l/u_sysgen_wrapper/U_sysgen/sysgen_dut/fpga_x0/dds_v5_0/com
p0.core_instance0/N2463)
Unable to pack register
Top_l/CustomLogic_l/u_sysgen_wrapper/U_sysgen/sysgen_dut/fpga_x0/dds_v5_0/com
p0.core_instance0/BU333 because of connectivity restrictions. The register
failed to be packed in FFX for the following reasons: The signal
Top_l/CustomLogic_l/u_sysgen_wrapper/U_sysgen/sysgen_dut/fpga_x0/dds_v5_0/com
p0.core_instance0/N1146 can not use the BX pin because of other resources in
the slice. The register
Top_l/CustomLogic_l/u_sysgen_wrapper/U_sysgen/sysgen_dut/fpga_x0/dds_v5_0/com
p0.core_instance0/BU333 is unable to use the F LUT as a route through. The
register failed to be packed in FFY for the following reasons: The register
Top_l/CustomLogic_l/u_sysgen_wrapper/U_sysgen/sysgen_dut/fpga_x0/dds_v5_0/com
p0.core_instance0/BU331 already occupies FFY. Please correct the design
constraints accordingly.
 

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