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Recent content by oldMan62

  1. O

    Number of digits for PCell parameters

    The problem I see is that layout already assumes microns for a dimension therefore the size in the form means 900 micro microns. Use parameter type=float. Units=none QUOTE=mult;1205104]Hi all. I designed PCell using SKILL (for example "Seal ring" with three parameters: "Description", "X Die...
  2. O

    Cannot generate ahdl_include in netlist by ADE

    If the view of your macro is "veriloga" then "veriloga" needs to be in the switch view list, not "ahdl". Or is this and "include" file?
  3. O

    Problem with Assura in IC614

    Assura is a separate install from IC61. In a terminal window type "which assura". If it doesn't return a path like: someInstallPath/cadence_assura04.12.005/tools/assura/bin/assura it is not installed or your path variable doesn't include it.
  4. O

    Analog layout: Length & Width of MOSFET

    As simply as possible when a MOSFET is conducting current and all other variables are held constant the drain current is proportional to the ratio W/L
  5. O

    urgent- help-pll design urgent

    Look at the Cadence supplied aExample library located in "cadence install path"/tools/dfII/samples/artist directory
  6. O

    [SOLVED] reduce left and right sid eof poly using skill

    The following will work for rectangles: Select the shape and execute the following commands in the CIW obj=geGetSelSet() lx=xCoord(lowerLeft(car(obj~>bBox))) ly=yCoord(lowerLeft(car(obj~>bBox))) rx=xCoord(upperRight(car(obj~>bBox))) ry=yCoord(upperRight(car(obj~>bBox)))...
  7. O

    [SOLVED] how can I generate multiple layout with a for loop in SKILL language?

    Use this for your cell names: strcat("test", pcExprToString(i))
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