Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
I can' find a entry for Questasim in the **broken link removed**
So I choosed Modelsim to send my Bugreport but my mail got rejected:
Failed to create SR or associated activity:
Cannot create SR, Contact is not found in the system: <MAIL>
I...
A new Update, I've created a new minimal example:
module min(clk, inputValue);
input clk, inputValue;
always @(clk)
begin
end
endmodule
//-----------------------------------------------------------
module minout(clk, inputValue);
input clk, inputValue;
always @(clk)
begin
end...
A little update:
the Syntax error appeared several times while I've tried to handle the logic nets from the UPF. You can get rid of this behaviour with a new start of Questasim. I still don't know why this error appears.
back to the not visible logic net:
- I've done some tests. The logic net...
Hi
When I try a to create a logic net, to connect a power management controller to another component (both written in verilog), I'm not able to see the created net in the schematics view.
The UPF-file were interpreted without any errors (I've also double checked the naming )
The section from...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
