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Re: two puzzles about the "M" of mos model in hspi
In the second question the answer is yes, AS AD etc are multiplied. Not exaclty like in real life where the transistors share the drain or source.
Re: Analog IC Design at 90nm
There is a lot of analog design in 90 and now 65... especially in SOC. There are problems but the principles are exacly the same. Anyway fabs offer high voltage devices with thicker oxide so ... it depends what you call 90nm :).
vt nmos
AFAIK all fabs offer zero Vt and is free.... is not an added mask. It is very used for caps because they are more linear. If you make a cap wioth normal device the value of the cap varies wildly around the Vt.
Monte Cralo is one solution (the best).
The other way is to put DC sources at each pair of transistor. Get matching data from the fab and see the influence.
Re: negative capcitance!!
What simulator gives you this? Hspice does not give you negative caps.... if you are sure the design is right, you can take the absolute value.
Re: about Q factor...
You are not clear. In LPF you don't want ringing and you keep Q low. In BP ringing and oscillation is what you want, high Q is good... very different purpose.
Yes, this will decrease your CM error. but you should be really carefull about the stability in common mode. And, gain comming at the expense of BW, is a trade off.
siemens denmark salary
Not really. I send you in some forgotten vilage or small city (Tulsa, Oklahoma comes to mind, or think Alabama) and I pay you a lot comparing to the prices there... guess what, you'll still get depresed. There are lots of people who care about this, and lots of peolple...
Yes, it is a great city by american standards. I don't know if I could name more than 2-3 places better than this in the whole US. Now, if you start to compare with europe, is different, but we are talking about US. Universities make a city good: young and cultivated people, bars, restaurnats...
It will but maybe not much. BTW, 7t is for 10 bits as i remember, for 12 you need more. Now, you should just compute how much it takes for your op amp to slew over the entire range. From C*U=I*t, I is the currnet flowing in the cap, C is load cap, U is maximum output variation (max. amplitude...
nwell resistor layout
I just don't get it, everybody seems to belive that techology should be kept a secret but the keep asking questions about sizes.
Anyway:
1) You put caps and resistors over (not "in") Nwell to decrease the noise injected to/from substrate. You know better if that is an...
Re: About DNL problem
There are not two definitions, it is only one, the second. The other one is called Maximum DNL. It is true though that people forget sometimes to put maximum in front when they characterize chips (in datasheets).
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