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Recent content by o2blom

  1. O

    ESD shock on frame ground causing FPGA problems

    For anyone else seeing this type of issue I found this article online that does a pretty good job explaining what might be happening **broken link removed**
  2. O

    ESD shock on frame ground causing FPGA problems

    FvM, I agree with your analysis. I'm not sure how to suppress it at the board interface though. I have two 2.5cm wide islands of chassis-ground on the PCB's front and rear panel, with about 5mm separation from the main digital ground. These can be connected to the main ground using four 1812...
  3. O

    ESD shock on frame ground causing FPGA problems

    Barry, Previously I have comfortably been enjoying the predictability of digital designs (Verilog), but now I'm being thrown into ESD & Surge "black art". Quite frequently it doesn't make any noticeable difference adding TVS diodes or MOVs, which is very frustrating. If you know of any good...
  4. O

    ESD shock on frame ground causing FPGA problems

    Hi Barry, The board is already in an aluminum chassis, (slightly bigger than a VHS tape) with metal on all sides. The ESD is injected on the frame ground pin of the power terminal block on the rear panel. There are some openings on the front and rear panels for dip switches and connectors...
  5. O

    ESD shock on frame ground causing FPGA problems

    Hi There, I have a pretty simple 4-layer board with strange ESD problems. Using a ESD gun and shocking the frame-ground terminal of the power terminal block the FPGA configuration will sometimes get corrupted. I'm stumped because, as far as I know, the goal of ESD protection is to get the...
  6. O

    PCB layer cut-out underneath standard 5x7 oscillators

    Hello There ! Is there any good reason to cut out all the layers underneath a standard 5x7 (25mhz) oscillator device ? I've seen this done in some designs, but currently space is very limited so I would like to route signals below it. Thanks, /Otto

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