Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
So do I have to create a schematic view and then add the file somewhere in ADE L ? I did not understand the "right click on the test name in the data view". is this available in ADE L ?
I have .scs netlist. I want to run the simulation specified in the netlist. How to run ? Any leads would be appreciated. I tried to just load the file like it is done for ocean script (load "filename.scs") is it the same for netlist or any other method ?
Adding to my OP, what are the key points to be considered while sizing when I go down the technology. For example a transistor has W/L = 4 for 180nm technology (W=720nm and L=180nm). If I want to design in 45nm, should I increase the width by 4 to 128nm or increase it further as the technology...
This is a general question on sizing of transistors. I would like to know if there is any generalized way to start designing a circuit (deciding on transistor sizes) for all the applications. I know the length is same and depends on technology. But how to adjust the width ? Does the sizing or...
I think that is possible. May be not today but sometime in future.
- - - Updated - - -
I think that is possible. May be not today but sometime in future. @ThisIsNotSam
I would like to know if there is any synchronous up counter which increments at for every 10 ps (At pico second level). Basically a high precision Counter. I tried using 2 D Flip Flops which are made up of 3 input Nand gates. It is working properly for nanosecond precision but not for picosecond...
Hello. This method works fine but if I add a voltage source to the gate of MOS, it alters the netlist. I found somewhere that using Subcircuit which has parametric dependent Vdc inside, the netlist is not altered. Anyone know what a subcircuit is and how to create it.
Hello all,
I found a different way. Instead of changing the .pm file, i can add a voltage source to the base of MOSFET and sweep the voltage source ? this would work ?
Yes. You are right. But I am working on Aging. So to check my Aging behaviour, do I have to request another model from foundry with changed Vth values ?
What is the coding used in .pm file ?
I want to check the output voltage of a block made up of pMOS and nMOS for different threshold voltages. I am using .pm file as the model file. pMOS and nMOS are used from analoglib (nmos and pmos). Can someone help if I can specify an array in the .pm file for vth parameter? Or what is the way...
Re: Verilog A error for 4 bit serial in parallel out shift register
I changed and got the below error..
Error found by spectre during AHDL compile.
ERROR (VACOMP-2259): "dout3 <+<<--? temp[3];"
"/tmp_net/libraries/mse5/SIPO_10_new1/veriloga/veriloga.va", line 38:
syntax error.
Hello,
I am planning to write a verilog-A code for a 4 bit serial in parallel out shift register. But I am getting an error. Any idea about this ?
Here is my code..
`include "constants.vams"
`include "disciplines.vams"
module SIPO_4(din, clk, reset, dout0,dout1,dout2,dout3);
output...
RelXpert Simulator working principle in background(Not the exact simulation steps)
Hi All,
I would like to know more about RelXpert simulator and how it calculates the age. What is the basic principle RelXpert works on. Anybody with any inputs on this or any good materials or links to know...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
