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Recent content by nmg

  1. N

    how do i write a dual port memory code in vhdl?

    yup! now that i've made my data and address only 8bit and the counter ranging from 0 to 255, i have no errors, but when i run it it is getting stuck in line 37 (mem(conv_integer(addr1))<=data1;) line 37 is my write statement, why do yo think its not getting any further than that?
  2. N

    how do i write a dual port memory code in vhdl?

    ok, this code is what i've written entity wriread is Port ( clk : in STD_LOGIC; en1,en2 : in STD_LOGIC; we1,we2 : in STD_LOGIC_VECTOR (0 downto 0); data1,data2 : in STD_LOGIC_VECTOR (31 downto 0); addr1,addr2 : in STD_LOGIC_VECTOR (15 downto...
  3. N

    how do i write a dual port memory code in vhdl?

    basically i want a dual port ram write/read code with address counters and the above states(initial,input,read,write states) can you please provide the code for it.?
  4. N

    how do i write a dual port memory code in vhdl?

    ok i have this code with states is it correct? entity bram is port(clk:in std_logic; en1,en2:in std_logic; we1,we2:in std_logic_vector(o downto o); data:in std_logic_vector(31 downto 0); addr:in std_logic_vector(15 downto 0); dataouta,dataoutb:out...
  5. N

    how do i write a dual port memory code in vhdl?

    ok i do understand the counter but my question is how do i use the counter in the code that i've mentioned before?? do i just add the count statement before the read/write statement?
  6. N

    how do i write a dual port memory code in vhdl?

    can you please send an example code in which address counter are a part of read/write code.
  7. N

    How to write data to address array of dual port RAM using VHDL?

    i am trying to get a pure simulation model along with the address sequence,as you mentioned earlier i can do that by using state machine,but i dont know how.
  8. N

    how do i write a dual port memory code in vhdl?

    thanks a ton!
  9. N

    How to write data to address array of dual port RAM using VHDL?

    am sorry i am new to this, well right now the code that i am using is as follows library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity true_dual_port_ram is port (clk : in std_logic; we : in std_logic; en : in std_logic; addr1 : in...
  10. N

    How to write data to address array of dual port RAM using VHDL?

    hi tnx but how do i use a state machine? can you please provide a code for it? please.
  11. N

    how do i write a dual port memory code in vhdl?

    hi tnx but keeping the states aside a simple read/write code how do i write it with address counters? say this is my dual port ram code library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity true_dual_port_ram is port (clk : in std_logic; we : in...
  12. N

    How to write data to address array of dual port RAM using VHDL?

    Re: VHDL Dual port Ram the above code is fine, but what if i have to write many data ex.data which is (7 downto 0) into address which is(3 downto 0)? then what do i do?
  13. N

    how do i write a dual port memory code in vhdl?

    can someone please guide me to write a write/read code for dual port memory in vhdl, i want the code to contain reset state, input state, write state and read state.and also i would want to include counters for address.
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