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Recent content by njr@1

  1. N

    What do you mean by job in NCX

    Dear all What do you mean by Job in liberty NCX - synopsys library characterization tool. Also what do combinational arc ? Thanks a lot in advance
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    NCX library characterization for flip flops

    Dear all I am trying to characterize the std library cells for 0.5V using NCX. I am having trouble with the flip flop cells. While in case of combination cells can i add all of them in the same do loop in the ncx.opt file and run the .cfg file. Do i need to set any argument true to make that...
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    NCX tool understanding time index

    Hi i am trying to characterize the std lib for 0.5 v. I believe we need to modify the index for timing . Please guide how to go about doing that ? Thank you
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    NCX tool indices file issue

    The indexes are the values for input slew to calculate or characterize the delay timing of the cells.
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    Understanding FO4 intutively

    Dear all, Please help me understand the the FO4 intuitively. Why is it used everywhere in case of timing analysis ! Thank you
  6. N

    Feedforward/Linear Structures

    Dear All, I am confused on these two terms in a circuit. When do you call the path is feed ward and when do you call it a linear path. Please let me now. Thank you
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    Synopsys Design Compiler

    yes. There are valid path.
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    Synopsys Design Compiler

    create_clock "clk" -period 5 [get_ports clk] in this way.
  9. N

    Synopsys Design Compiler

    Dear all When I try to synthesis the Design ware example in DC and give the clk some period why am I not able to see the clk period in the timing report or the report_qor! it says critical path slack as uninit and critical psth clk period as n/a ! Please let me know. Thank you
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    Oordinated Rotation Digital Computer(CORDIC)

    ya sure, In case of the example in opencore, how do you think it is implemented ? Thank you
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    Latch growth factor (LGF)

    HI sorry, LGF is latch growth factor
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    [moved] Synthesis RTL in synosys DC

    Dear All, When we synthesis in Design Compiler with different clk period why does the critical path changes with the change in clock period ? So does the area when viewing the report using report_qor. Please help me understand this
  13. N

    Latch growth factor (LGF)

    Dear All, I am new to this domain of VLSI, and stuck with LGF. Can you help in understanding this term more intuitively . Thank you
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    Oordinated Rotation Digital Computer(CORDIC)

    Dear all, In case of CORDIC been implemented digital , would it have a feedback path ? can it be considered to have a feedback structured micro architecture ? Thank you
  15. N

    Using Design Ware (synopsys) Example

    Dear All, How to confirm if the re timing has worked in example (DW_mult_pipe Stallable Pipelined Multiplier) given in design ware library? There are two description as in before pipeline re timing and one after pipeline re timing, but while using balance register in synposys DC it does not...
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