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Recent content by nitin_ndg

  1. N

    Could we write "CLK" based statements in packages?

    Re: Could we write "CLK" based statements in packa Yes you can use . i have used clk in PKG. Even i have made my own function "rising_edge" and falling_edge". it works....
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    Problem with using while loop in VHDL

    Re: While Loop Y he is right
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    Resources to learn DSP algorithms

    Re: Beginner............ go to analog device's web page and find Book DSP for engineer and scientist. its very good book. if dont find then let me know ....
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    Why is there different ground in a circuit?

    Hi marco antonio There can diffrent grounds in your circuit. its all depend on the verity of component's VCC supply. Say for Example If you use a chip that works on 3.3v then circuit will have a groung reference of 3.3v as all the cureent will return to this referrence only. like wise if...
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    Does modelsim support systemverilog simulation now?

    modelsim system verilog license Hi Deepak Plz up load some pdfs on system verilog
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    Tutorial for starting Cypress CY7C68013 USB controller

    Re: CY7C68013 USB hi i am also looking for CY7C68013 USB's example ..is any one of u have some step by step floe plz help me Nitin
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    How to do post-synthesis simulatiion with Xilinx ISE simulator in ISE 8.2?

    Hi Can any one help me , how to do Post synthesis simulatiion with Xilinx ISE simulator in ISE 8.2. this ver of ise has options like "Behaviour simulation" "synthesis and implemetation" etc..... i am able to do Behav Sim and post P&R simulation but not Post Synthesis... p nitin
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    Computers as components .......

    Hi Does any one has this book Computer as components principles of embedded computing system design Wayne Wolf (morgan Kaufmann Pub.) i badlly need this book nitin
  9. N

    Why setup time is needed?????????

    Hi, thanks JFrensch what about setup time voilation??????
  10. N

    Why setup time is needed?????????

    Hi avimit Needed ??? meas....there is a perameter Tsu. this time relation has to be maintain with respect to clk.... Can any one tell me what is theory behind hold time.. thanks
  11. N

    Why setup time is needed?????????

    What ? i didn't get
  12. N

    Why setup time is needed?????????

    Hi Swapnil_vlsi what u told is defination of setup and hold time. my question is theory behind Tsu and Th. Tsu needs to charch the cepacitor .. next Q. is why Th is requored...
  13. N

    Need a VHDL code for 16 bit counter with up range and low range

    Re: vhdl for counter Plz tellme ......is it ans ur question or not.... may i help u any more...
  14. N

    Need a VHDL code for 16 bit counter with up range and low range

    Re: vhdl for counter You can modify for need by adding a signal say "Up_down". -------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity counter is port ( clk:in...
  15. N

    when clock and reset are on the same clock edge .

    Do design sync reset in VHDL write Presess(clk) begin if clk'event and clk='1' then if reset='1' then D<='0'; else D<=Q; end if; end if; end process; ----------------------------------------------- Do design Async reset in VHDL write Presess(clk,reset) begin...
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