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just a note or two:
splitting FSMs is different than state enumerations.
on splitting FSMs:
https://asicdigitaldesign.wordpress.com/2007/09/08/a-concise-guide-to-why-and-how-to-split-your-state-machines/
on FSM enumeration...
If you got a lot of wires criss crossing the chip it might cause congestion problem (not enough space for a lot of wires that need to go through a specific area).
Be especially careful near SRAM blocks since a lot of times routing above them is not allowed and they create a "hole" in the floor...
in some special cases combo loops are very beneficial.
check this link out:
https://asicdigitaldesign.wordpress.com/2008/03/07/cyclic-combinational-circuits/
ND
https://asicdigitaldesign.wordpress.com/
fpga dual edge ff
one could create a dual edge flop as described here:
https://asicdigitaldesign.wordpress.com/2007/07/31/the-double-edge-flip-flop/
or here:
https://asicdigitaldesign.wordpress.com/2008/09/22/another-look-at-the-dual-edge-flip-flop/
ND.
https://asicdigitaldesign.wordpress.com
10bit LFSR design
There is a proof in GF theory (the math behind LFSR) that for any given length, there exists a maximal length LFSR - i.e. one that is 2^n-1 long
ND.
https://asicdigitaldesign.wordpress.com/
Please try reading this:
https://asicdigitaldesign.wordpress.com/2007/08/09/driving-a-clock-frequency-signal-from-a-register/
maybe it will help you.
It describes a way to drive clock frequency signal without having the clock in the data path.
ND.
https://asicdigitaldesign.wordpress.com
10bit LFSR design
All you need is here (page 7):
https://www.eng.auburn.edu/~strouce/class/elec6250/LFSRs.pdf
ND
https://asicdigitaldesign.wordpress.com/
carry skip adder vhdl
your answers are in this book:
https://www.amazon.com/CMOS-VLSI-Design-Circuits-Perspective/dp/0321149017/ref=pd_bbs_sr_1?ie=UTF8&s=books&qid=1228251816&sr=8-1
ND
https://asicdigitaldesign.wordpress.com
just to add a few words.
FvM is complete correct - no reset is really necessary. actually in some applications it is recommended to do it without a reset! (because the clock might only be available in a later stage and the asynch reset removal is aligned with a reset synchronizer to the clock...
Re: Minimum Of N Numbers
The complexity of the problem is (compare delay)*log2(N)
you are basically performing a binary tree (hence log2(N) ) of compare operations (each costing a "compare delay")
I have no idea how much of the logic you can compress into a single clock cycle.
but make a combo...
Whenever you encounter a problem like "design a divide by ..." this is how you solve it.
1) draw original clock
2) draw target desired clock
3) watch if the new desired clock can be derived from the original clock - this means if the ALL rising edges and the falling edges of the new clock ALIGN...
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