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Hi everyone,
When we want to calculate ADCs sampling capacitor size we choose C such that thermal noise level is less (or equal) than quantization noise
KT/C<Δ2/12
Which leads to
C>12KT×22b/VFS2
My question is that if "C" here is the total capacitance of the capacitor array or unit cell...
I have attached an image of the pin properties.
I looked in TSMC 65nm library but couldn't find anything that looked like a dummy resistor (LVS RES as you said)!
The connectivity is also clear.
A few more notes about this question:
1- I'm trying to draw a simple MOM capacitor
2- Top plate consists of M5 and M7 which are connected through vias
3- Bottom plate is made up of M6
This is my question:
When I draw the capacitor that I explained above, and after running LVS, I get "Nothing in...
Hi,
I'm trying to design a customized capacitor in Cadence, IC16. I use TSMC 65nm PDK, and the extraction tool is Calibre. What are the layers that make the extraction tool understand that my device is a capacitor?
Thanks
Thanks. I have seen that in many papers for SAR ADCs comparator is connected to VDD, although, as you see above it can work properly for much lower supply rails, It's a bit confusing because lowering the supply can definitely lower the dynamic power consumption, so I thought there should be...
Hi
I have simulated a simple dynamic comparator and it is working properly with input voltages beyond the supply rails, as I know we don't use input voltages beyond supply rails, Would you please explain why we cannot use inputs beyond the supply rails when the circuit is working properly...
Re: Conventional charge redistribution ADC
I really don't know ,since these equations are written in the steady state and in the manual it is written that C is discharged when s4 is connected to ground:
in TI Manual we have this:
so for the configuration below I write:
V1*3C/2=V2*C/2
and V1+ V2 = Vref
so : V1= Vref/4 and V2=3Vref/4
so I think according to grounding the MSB we should write the out pot coltage like this: Vc=-Vin+Vref/4
but sounds that TI Manual has added Vref/2 from previous...
I know charge conservation (Q1=Q2 or C1.V1=C2.V2), It is the most basic equation we should know to analyze charge redistribution or circuits involving capacitors, I am saying that I think it is not used properly, I have edited it like below:
Sorry, I don't understand, Is that Q1=Q2? Because I do understand that, But the manual is some how troubled, If you take a look Equations written in
the pictures do not match the situation of bit cycle. I have checked it with these articles too:
"All-MOS Charge Redistribution Analog-to-Digital...
Hi
I cannot understand why in the comparison of the second MSB, Input voltage to the comparator would be :
While the charge on MSB has been discharged and there should be no Vref/2 anymore.
And vise versa , When MSB has not been discharged the input voltage to the comparator is:
While...
UART interrupt not returnning to the main programm (loop)
Hi
I have written this code for UART interruption with basic language for basscom but when the first interrupt occurs it does not return into the loop and it displays HI over and over again on the lcd , Would you please help me with it...
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