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Hello,
I am trying to back-annotate delays using $sdf_annotate file in Icarus Verilog . The simulation completes with a few warnings but when i view the waveforms , no delays are prepesent.
Anyone had any luck in the past with this tool and back-annotation?
Thank you
Thank you for your input.
The reason I was trying to do that is because the address of the SRAM is generated from another (external ) circuit. This external circuit shares though the same clock as the SRAM. The time it takes for the external circuit to produce the adress ( output ) is lets say...
Hello Brad,
Thank you for your input. However I am looking for a completely digital solution that will be synthesized. If custom solutions were to be used, I have an analog delay line that can be used.
I tried to use this constraint, but it had no effect ( it did not insert any delay units/buffers). Also, i thought that constraint was used to "emulate" different duty cycles.
Maybe i did not explain it well.
I am talking about a read operation from the RAM.
So the mentioned control block at the rising edge of the clock generated an address at its output . This is the address that should be read from the RAM at this clock cycle and fetch the address contents. The...
In my case, a control block generates at the rising edge of a "clock" an address that is fed at a RAM. The RAM accesses the address and propagates the contents at the output. This exact output needs to be read back from the control block in the same clock cycle.
So I think that this is a special...
Hello KlausST,
Thank you for the reply. The thing is that the data input is lets say 400ps delayed in relation to the arrival time of the "clock" signal.
My first idea was indeed to use the opposite clock edge in order to have enough setup time. However, the output of the sequential block needs...
Yes, i need to make sure that the data are captured at the correct time.
Unfortunatelly I dont think i can add delay at the data path, so is there a way to force delay at clock path?
Hello everyone,
I have a design where on the top level I have a clock signal as a port and I want to make sure it arrives with a delay at a specific pin inside the hierarchy.
I tried something : set_min_delay 0.5 -from CLK -to hier1/CLK (where hier1 is the module and CLK is the module's clock...
Hello everyone,
Sorry if I missed the topic and the question is already answered.
I want to simulate the phase noise contribution of an MMD used in a frequency synthesizer. For the purpose of simulation, the division is integer ( divide by N ). I use PSS and add Beat frequency to be Fvco/N (...
Hello everyone,
I want to simulate the phase noise of a multi modulus divider at the feedback path of a fractional frequency synthesizer.
The input frequency of the divider , which is the output of VCO, is 16G. The divider then divides this value with an average ratio of 200, which is controlled...
Hello everyone,
Suppose we have a Fractional-N frequency synthesizer employing an MMD + 3rd order MASH loop. If we want to divide by the fractional value 100.XX ( where XX = fractional value ) , the MASH will instruct the MMD to divide by values between 97 - 104.
My question is , which is the...
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