Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Hello
I am designing Dynamic SBOX for AES. I have designed it for encryption as- normal AES Sbox xor Roundkey (127 down to 120) but for decryption I need inverse of that so, I am not getting how to inverse a 16*16 matrix.
Because if I do it directly then i'l get Inv Sbox xor roundkey(127 down...
Hello
I solved the mix column step problem and the particular block is working fine, but still not getting the correct output of top module and I am not able to attach the single top level .vhd file so, making a zip file of that single vhd file and attaching it. please check it and help me.
Hello
Thanks for your reply. I am simulating it in ISE 9.2 so, I am just generating Test Bench Waveform. I am getting results for encryption so, I think there is some problem in code. please help me in finding the error.
Hello
I am doing my thesis project as VHDL Implementation of AES-128 algorithm. I have done the encryption and decryption using loop unrolled architecture but it is giving me high resource utilization. So, I am trying it by using State Machine. I have taken 4 states as RESET1, RESET2,IDLE...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
