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First of all.. thanks for your reply.
I want to clarify the layers:
1) Red - Diffusion
2) Blue - Poly
3) Turquoise - Contact
4) Pink/Magenta - P Implant
5) Gray (hard to see -> around NTAP; over and under PMOS devices) - N Implant
6) White - NWELL
7) thin White (covers inner devices) - DNW
- -...
Good morning,
I thought if I have an diffusion layer that shares area with a P-implant I get P+ at the shared area. Without diffusion I get P-. Is that wrong? :roll:
Edit: the white lines are the NWELLs. Pink is P-implant. Gray is N-implant (hard to see on the picture).
My DRC is clean. There...
Thanks for the reply:
Yeah it looks like. On metal there is for sure no connection. How can there be a connection if I have the P-implant/diffusion that forms P+ and N-implant/diffusion that forms N+ inside a NWELL?
- - - Updated - - -
For me this short connections make no sense. Yes DRC is...
Hi,
I have a problem concerning layout. My PMOS transistors are P-cells and are grouped depending on there function. Every group shares a NWELL and an isolation ring (PTAP and DNW). The NWELL should be taped to VDD near every transistor to get proper bulk connections. This is how i wanted to do...
Hello guys,
I have some problems in modelling some behaviour of an analog I/O block. Applying a signal to the input pad of this block causes the duty cycle at the internal signal (output) to decrease from 50 to 30% at the worst corner. I want to modell this behaviour but don't know what is the...
If you want to simulate it in time domain: Use an iprobe to monitor the complete current consumption of the OTA, average it with the average function of the calculator and multiply it with your VDD. You get the static + dynamic power consumption.
You need this metal layer underneath your CTM (Capacitor Top Metal) because the thin isolator is build on top of the metal. Otherwise the layout can not be fabricated:
http://amarketplaceofideas.com/wp-content/uploads/2015/03/XH018-MIM-Capacitor-Cross-Section.png
I guess you have an 6 Metal...
You are working on TSMC PDK I guess? Usually this Layer is used to form MIM Caps. It is a special layer that is used in process options that offer this kind of Caps.
Hi debdut,
thx for your answer.
As it's a big Array that has to match properly I wanted to make it as symmetric as possible. Therefore I added many NTAPs and a dummy structure around it (red). Area is no issue for this layout. The main task is to ensure that layout has as less impact as...
Hi experts,
as I'm not very familiar with layout and I intend to do my first one, I have some questions:
For my circuitry I need some matched serial stacked PMOS transistors with the bulk connected to the same node (VDD). During the design phase I used 4 terminal devices of the PDK.
This is...
Plenty of slides out there:
**broken link removed**
https://homepages.rpi.edu/~sawyes/Models_review.pdf
https://www.eecs.berkeley.edu/~hu/Chenming-Hu_ch5.pdf
BR
Lukas
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