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Recent content by nickwang1982

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    CEVA and Tensilica DSP for voice processing?

    Can someone give a comparison of ceva and tensilica dsp in voice processing application, such as VAD, voice trigger, in terms of area, power consumption, process technology, price, usability, popularity, etc.? any examples? I just start looking at tensilica HiFi mini and ceva TL410, not much...
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    How to count number of positive edges of a signal in simvision waveform window

    How to count the number of positive edges between cursors? I remember I used this function long time ago, but I cannot find it now. I am using SimVision 08.20, is it because this version is toooo low?
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    how to implement digital trigger in a MCU based oscilloscope

    thank you for the reply. I have 2 more questions. 1. if I want to do some complex digital trigger, FPGA must be used, it that correct? 2. For external ADC, how can I interface it with an MCU which does not have FSMC or any standard parallel ADC interface(CMOS/LVDS)? Can I just program GPIO to do...
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    how to implement digital trigger in a MCU based oscilloscope

    Thanks for the reply. I know that people use FPGA or CPLD for digital trigger. I will do a FPGA (do everything in FPGA) scope later on. But now I am building a MCU version, so looking for reference from the commercial MCU based scope...
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    how to implement digital trigger in a MCU based oscilloscope

    I am trying to build a scope based on a MCU with PC to display waveform. The MCU integrates ADC, RAM and transmits captured and processed data to PC. The only thing I can think of to implement digital trigger inside MCU is that after each ADC sample, the core will read it and calculate if it is...
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    [Verilog] help! a decoder with unknown number of inputs

    Thank you for the answer. I see what you mean, so I have removed for-loop replacing with ruby //decode logic below assign x1 = (freq_1 > freq_2)? freq_1:freq_2; //compare the first two inputs and select the bigger one <% (1:NUM_INPUT-2).each do |i| -%> x<%=i+1%> = (x<%=i%> >...
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    [Verilog] help! a decoder with unknown number of inputs

    Here is my problem. I have unknown number of inputs (all with 3-bit wide), depending on the system configuration. I want to design a decoder to select the input with largest value as the output. So I am using embedded ruby here, so that the configuration can be passed to RTL. Here is my design...

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