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Recent content by netreg

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    Need help with fifo verification

    verification of async fifo hey yes thank you ppl for the help
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    Need help with fifo verification

    verification + fifo + bfm + monitor Thank you Ajeetha Added after 11 minutes: @skyfaye Regarding the area of scoreboard, monitor and checker. What exactly is the difference between them. Scoreboard : stores the input value (write value) . Monitor: captures or stores the output value(read...
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    Need help with fifo verification

    verification of a fifo hey thank you..
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    Need help with fifo verification

    fifo verification I am new to verification. For verification of fifo, the components required that I have identified are testbench, DUT, bus function model and scoreboard. Is there a difference between testbench and testcase? And can somebody elaborate on the Bus function model for sync fifo...
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    RTL Source code for FIFO - pointers to sources

    source codes on rtl Hi Paul, Checked the ASIC-world and found examples about verification of FIFO... Thanks Added after 6 minutes: hi Pini_1 Thanks
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    post synthesis simulation of netlist - ncsim

    ncsim instance unresolved Thanks Paul...
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    RTL Source code for FIFO - pointers to sources

    rtl code Can somebody suggest if RTL source code for simple designs like FIFO or so will be available on net?. If so suggest some links or sites from where I can download them. Thanks
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    post synthesis simulation of netlist - ncsim

    bit blasted ports+sdf Thanks...I am using palladium for synthesis. Is there an sdf file generated using the palladium or is there some other compiler using which I need to generate the sdf file.
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    post synthesis simulation of netlist - ncsim

    post synthesis simulation need help in post synthesis simulation of netlist. I am new to this area. Can somebody tell how to go about the simulation of netlist. I tried simulatiing by using ncsim but encountered error in ncelab : CUVMUR instance of design unit unresolved. Also is there some...

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