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Recent content by needhelp123

  1. N

    One cycle delay vhdl

    I'm required to short the 2 pins with a wire for the LED to light up. So, initially the LED shouldn't light up (but it does now), until I short the 2 pins together. - - - Updated - - - How do I go about it?
  2. N

    One cycle delay vhdl

    However in the simulation you gave, 'data_in' is always '1'. Is there another way to make receiving = output2 without internal altering of the code as I have to do it externally via output and input pins?
  3. N

    One cycle delay vhdl

    Is it possible to not make data_in always '1' ?
  4. N

    One cycle delay vhdl

    Then how can I make receiving the same as output2 ?
  5. N

    One cycle delay vhdl

    The LED still doesn't turn off when I did not short the 2 ports. It should be offed, and the LED will only light up when the 2 ports are short together
  6. N

    One cycle delay vhdl

    I still couldn't get the one clock cycle delay. It makes no difference from the code I've given, the LED will still light up even though I didn't connect the wires. It should only light up when I short the pins - - - Updated - - - I need 1 cycle delay on the dataout
  7. N

    One cycle delay vhdl

    They state that it is a Misspelled variable, signal or procedure name?. Do I have to declare any signal?
  8. N

    One cycle delay vhdl

    In need of help, I have a program here which I need to submit next week. I just need to add in 1 cycle clock delay but I have no idea how. This is my code Library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; use IEEE.std_logic_arith.all; ENTITY fpga is port( data_clk...
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