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Recent content by needforspeed

  1. N

    dc offset of a PD cell. need help!!!

    we have used auto-zeroing in the circuit, so offset of opamp should be cancelled. And I don't understand how resistance can cancel offset. could you elaborate it?
  2. N

    dc offset of a PD cell. need help!!!

    Hi guys, A PD(proportional plus derivative) cell was designed and fabricated, as shown in the following figure. Ideally, we have Vo[n]=-((C1+C2)/C3)Vi[n]+(C1/C3)Vi[n-1], which is what we get in simulation. However, measurement result is Vo[n]=-((C1+C2)/C3)Vi[n]+(C1/C3)Vi[n-1]+Con. Con is a...
  3. N

    How to view the layout contents of the instances?

    how to use opc_block layer options---->display------>display levels--->start 0 and stop 32
  4. N

    about layout match of asymmetric transistors

    Hi, I have an operational amp implemented by using asymmetric transistors. I guess it's not a good idea to share drain and source in a pair of transistor concerning match. Do you guys have any idea about layout matching of asymmetric transistors?
  5. N

    cm voltage at integrator input SDM

    You can define common voltage by your self. It should be same as common voltage of your integrator.
  6. N

    pll jitter in papers - not specified which jitter it is

    Re: pll jitter in papers I think it's not a problem of peak to peak jitter or rms jitter. All of 3 metrics can be described as peak to peak value of RMS value. One should clarify that it's cycle to cycle jitter, period jitter or TIE.
  7. N

    pll jitter in papers - not specified which jitter it is

    pll jitter in papers Hi guys, as well known, there are 3 commonly used jitter metrics: cycle to cycle jitter, period jitter and time interval error. I have read a lot of paper about PLL. Most of them give measured jitter of PLL clock. But, few of them specify what kind of jitter it is. I think...
  8. N

    How to estimate delay of a clock signal through a 20cm cable

    clock dealy Hi guys, How to estimate delay of a clock signal go through a cable of about 20cm. If the clock frequency is doubled, will the dalay be larger? Thanks
  9. N

    question on PLL spectrum - two large and wide peaks

    pll spectrum I have a PLL works at 160MHz. The reference is 10MHz and bandwidth is about 200khz. The spectrum of output was got by using FFT. Several reference spurs can be seen on the spectrum diagram. This is due to non idealities of the charge pump. What I don't understand is that there are...
  10. N

    phase jitter, absolute jitter and tie

    absolute jitter what's difference among phase jitter , absolute jitter and TIE?
  11. N

    phase jitter , absolute jitter, TIE - what's the difference

    phase jitter vs TIE what's difference among phase jitter , absolute jitter and TIE?
  12. N

    phase noise to jitter- results are different from expected

    phase noise to jitter hi, I simulated my PLL's phase noise at behavior level and got a closed-loop pll phase noise curve. Than I tried to integrate the phase noise to get phase jitter and period jitter. The following matlab routine is used to convert phase noise to phase jitter and period...
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    Confusion about conversion from phase noise to jitter

    maxim phase noise jitter conversion What's the meaning of the bandwidth of interest? when we get jitter by integrating Phasenoise, how can we choose an integration interval?

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