Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Hi,
I am trying to unfix all the placed instances in my design and planning to do a refine placement to resolve violations due to overlapping. Please let me know the command that I should use to unfix all my instances. ( there is an option for unplacing instances "unPlaceAllInsts" linkwise do...
Query in transition delay after clock tree synthesis
Hi,
I am new to physical IC design and I am working on CTS now. After CTS when I checked the clock transition time, it seems that rise transition time is different from fall transition time. Can anyone tell me why its different?
Thanks!
IR drop can be minimized (it cannot be avoided totally). We can reduce the IR drop by introducing more power sources in your design and by properly constructing your power grids.
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
