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i m currently doing the layout for a pcie add in card using a 4 layer board.
the high speed differential Rx and Tx (propagating till 2.5GHz signals) are not placed in the same layer at the golden finger connector.
please check the layout below:
top layer - red traces
bottom layer - blue...
Hie there,
I am working for a IC design house in Malaysia. Currently looking for a vendor to support wirebonding work and component population for our protoype boards.
If available, please drop a mail at nathan@keyasic.com
if you are routing a one layer board; then you need to make the traces connecting to the ground to be thicker. try to make all unused area in the board as ground copper area. try to make all traces connecitng to gnd as short as possible.
Re: what exactly dielectric thickness in 4layer stackup mean
the core layer has copper traces on the top and bottom to form the inner layers.
core is definately a dielectric; otherwise power plane and gnd will be shorted.
you have mentioned to use termination resistors? is it also the case for just a rising edge pulse?
i am not using a square/sinusoidal wave signal with fixed frequency.
SI/ High Speed Design Sifus,Mahagurus,
I am quite new to high speed design. I am currently designing an evaluation board to charecterize my IC.
I need to input a rising edge and falling edge signal with rise time lesser than 0.1ns to my ic.
My question: Will the PCB trace being used be a...
Hie there,
I want to check the durability of the ESD internal circuit model in
my design.
Anyone done HBM test on bench to check Iesd vs current and Vesd vs
voltage. If yes, please advise on the test setup and which power
supply and measurement device to use.
h spice for windows
guess still not yet release any vista compatible hspice.
but for basic simulation; i m using 5spice. they have released a vista compatible version.
i am curious; currently i have been called up for an interview with a RF circuit design company.
one of the requirement sound like the below:
Experience in Digital Signal Processing circuit techniques and algorithm development for modulation, demodulation, filtering, and feedback control and...
i think due to the noisy eye; you cannot accurately perform BER testing or estimate sensitivity based on the eye diagram.
i experienced the same situation about a year ago.
first of all please confirm that the noise and jitter observed in the eye diagram is caused by design or layout issues...
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