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Recent content by natasha_a

  1. N

    Synopsys Design Compiler: Setting a maximum critical path delay on sequential circuits

    interesting. in the case that it is option 2, what additional constraints would be required? are these additional parameters/flags that I need to set? I'll check my logs and post an update. thanks!
  2. N

    Synopsys Design Compiler: Setting a maximum critical path delay on sequential circuits

    Yes, I've defined a clock period of 1 ns for all clocks in my module.
  3. N

    Synopsys Design Compiler: Setting a maximum critical path delay on sequential circuits

    I have a couple of designs written in Verilog that I'm trying to synthesize with Synopsys DC Compiler. Specifically, I would like to maintain a 1ns upper bound on my critical path delay (CPD) on my designs — I have been able to successfully synthesize these designs with yosys (open source RTL...
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